CY62157E_09 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – 8-Mbit (512K x 16) Static RAM

CY62157E MoBL^®
8-Mbit (512K x 16) Static RAM
Features
• Very high speed: 45 ns
• Wide voltage range: 4.5V–5.5V
• Ultra-low standby power
—Typical Standby current: 2 µA
—Maximum Standby current: 8 µA (Industrial)
• Ultra-low active power
— Typical active current: 1.8 mA @ f = 1 MHz
• Ultra-low standby power
• Easy memory expansion with CE₁, CE₂ and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in Pb-free 44-pin TSOP II and 48-ball VFBGA
package
Functional Description^[1]
The CY62157E is a high-performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL^®) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption when addresses are not toggling.
The device can also be put into standby mode when
deselected (CE₁ HIGH or CE₂ LOW or both BHE and BLE are
HIGH). The input/output pins (IO₀ through IO₁₅) are placed in
a high-impedance state when: deselected (CE₁HIGH or CE₂
LOW), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE₁ LOW, CE₂ HIGH and WE
LOW).
Writing to the device is accomplished by taking Chip Enable
(CE₁ LOW and CE₂ HIGH) and Write Enable (WE) input LOW.
If Byte Low Enable (BLE) is LOW, then data from IO pins (IO₀
through IO₇), is written into the location specified on the
address pins (A₀ through A₁₈). If Byte High Enable (BHE) is
LOW, then data from IO pins (IO₈ through IO₁₅) is written into
the location specified on the address pins (A₀ through A₁₈).
Reading from the device is accomplished by taking Chip
Enable (CE₁ LOW and CE₂ HIGH) and Output Enable (OE)
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on IO₀ to IO₇. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on IO₈ to IO₁₅. See the truth table at the back of this data sheet
for a complete description of read and write modes.
Logic Block Diagram
A₁₀
A₉
A₈
A₇
A₆
A₅
A₄
A₃
A₂
A₁
A₀
DATA IN DRIVERS
512K x 16
RAM Array
IO₀–IO₇
IO₈–IO₁₅
COLUMN DECODER
POWER-DOWN
CIRCUIT
BHE
BLE
BHE
WE
CE₂
OE
CE₁
BLE
CE₂
CE₁
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05695 Rev. *C
Revised November 21, 2006
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