CY62157EV30 Datasheet, PDF (1/14 Pages) Cypress Semiconductor – 8-Mbit (512K x 16) Static RAM

CY62157EV30 MoBL^®
8-Mbit (512K x 16) Static RAM
Features
• TSOP I package configurable as 512K x 16 or as 1M x 8
SRAM
• High speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin compatible with CY62157DV30
• Ultra low standby power
— Typical Standby current: 2 µA
— Maximum Standby current: 8 µA (Industrial)
• Ultra low active power
— Typical active current: 1.8 mA @ f = 1 MHz
• Easy memory expansion with CE₁, CE₂, and OE features
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in both Pb-free and non Pb-free 48-ball VFBGA,
Pb-free 44-pin TSOP II and 48-pin TSOP I packages
Functional Description^[1]
The CY62157EV30 is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL^®) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
Logic Block Diagram
reduces power consumption when addresses are not toggling.
Place the device into standby mode when deselected (CE₁
HIGH or CE₂ LOW or both BHE and BLE are HIGH). The input
or output pins (IO₀ through IO₁₅) are placed in a high
impedance state when:
• Deselected (CE₁HIGH or CE₂ LOW)
• Outputs are disabled (OE HIGH)
• Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
• Write operation is active (CE₁ LOW, CE₂ HIGH and WE
LOW)
To write to the device, take Chip Enable (CE₁ LOW and CE₂
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO₀ through IO₇) is
written into the location specified on the address pins (A₀
through A₁₈). If Byte High Enable (BHE) is LOW, then data
from IO pins (IO₈ through IO₁₅) is written into the location
specified on the address pins (A₀ through A₁₈).
To read from the device, take Chip Enable (CE₁ LOW and CE₂
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
appear on IO₀ to IO₇. If Byte High Enable (BHE) is LOW, then
data from memory appears on IO₈ to IO₁₅. See the “Truth
Table” on page 10 for a complete description of read and write
modes.
DATA IN DRIVERS
A₁₀
A₉
A₈
A₇
A₆
512K × 16 / 1M x 8
A₅
RAM Array
A₄
A₃
A₂
A₁
A₀
IO₀–IO₇
IO₈–IO₁₅
Power Down
Circuit
COLUMN DECODER
CE₂
CE₁
BHE
BLE
Notes
1. For best practice recommendations, please refer to the Cypress application note AN1064, SRAM System Guidelines.
BYTE
BHE
WE
OE
BLE
CE₂
CE₁
Cypress Semiconductor Corporation
Document #: 38-05445 Rev. *E
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised May 07, 2007