CY62157EV18_09 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – 8-Mbit (512K x 16) Static RAM

CY62157EV18 MoBL^®
8-Mbit (512K x 16) Static RAM
Features
• Very high speed: 55 ns
• Wide voltage range: 1.65V–2.25V
• Pin Compatible with CY62157DV18 and CY62157DV20
• Ultra low standby power
— Typical Standby current: 2 µA
— Maximum Standby current: 8 µA
• Ultra low active power
— Typical active current: 1.8 mA @ f = 1 MHz
• Easy memory expansion with CE₁, CE₂ and OE features
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in Pb-free 48-ball VFBGA package
Functional Description ^[1]
The CY62157EV18 is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL^®) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
The device can also be put into standby mode when
deselected (CE₁ HIGH or CE₂ LOW or both BHE and BLE are
HIGH). The input and output pins (IO₀ through IO₁₅) are
placed in a high impedance state when:
• Deselected (CE₁ HIGH or CE₂ LOW)
• Outputs are disabled (OE HIGH)
• Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH) or
• Write operation is active (CE₁ LOW, CE₂ HIGH and WE
LOW).
Write to the device by taking Chip Enables (CE₁ LOW and CE₂
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO₀ through IO₇), is
written into the location specified on the address pins (A₀
through A₁₈). If Byte High Enable (BHE) is LOW, then data
from IO pins (IO₈ through IO₁₅) is written into the location
specified on the address pins (A₀ through A₁₈).
Read from the device by taking Chip Enables (CE₁ LOW and
CE₂ HIGH) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins appear on IO₀ to IO₇. If Byte High Enable (BHE) is LOW,
then data from memory appears on IO₈ to IO₁₅. See the “Truth
Table” on page 9 for a complete description of read and write
modes.
Product Portfolio
Product
CY62157EV18
V_CC Range (V)
Min
1.65
Typ ^[2]
1.8
Max
2.25
Speed
(ns)
Power Dissipation
Operating I_CC, (mA)
f = 1MHz
f = f_max
Standby, I_SB2 (µA)
Typ ^{[2] Max} Typ ^{[2] Max} Typ ^[2]
Max
55
1.8
3
18
25
2
8
Notes
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” located at http://www.cypress.com.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V_CC = V_CC(typ), T_A = 25°C.
Cypress Semiconductor Corporation
Document #: 38-05490 Rev. *D
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised March 30, 2007