CY62157ESL_11 Datasheet, PDF (1/16 Pages) Cypress Semiconductor – 8-Mbit (512K x 16) Static RAM Automatic power down when deselected

CY62157ESL MoBL^
8-Mbit (512K x 16) Static RAM
Features
■ Very high speed: 45 ns
■ Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V
■ Ultra low standby power
❐ Typical Standby current: 2 A
❐ Maximum Standby current: 8 A
■ Ultra low active power
❐ Typical active current: 1.8 mA at f = 1 MHz
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Available in Pb-free 44-pin thin small outline package (TSOP) II
package
Functional Description
The CY62157ESL is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life (MoBL^) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Place the device
into standby mode when deselected (CE HIGH or both BHE and
BLE are HIGH). The input or output pins (I/O₀ through I/O₁₅) are
placed in a high impedance state when the device is deselected
(CE HIGH), the outputs are disabled (OE HIGH), both the Byte
High Enable and the Byte Low Enable are disabled (BHE, BLE
HIGH), or during an active write operation (CE LOW and WE
LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O₀ through I/O₇) is written into the location
specified on the address pins (A₀ through A₁₈). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O₈ through
I/O₁₅) is written into the location specified on the address pins
(A₀ through A₁₈).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O₀ to I/O₇. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O₈ to I/O₁₅. See the Truth Table on page 11 for a
complete description of read and write modes.
Logic Block Diagram
A₁₀
A₉
A₈
A₇
A₆
A₅
A₄
A₃
A₂
A₁
A₀
Power Down
Circuit
CE
BHE
BLE
DATA IN DRIVERS
512K x 16
RAM Array
COLUMN DECODER
I/O₀–I/O₇
I/O₈–I/O₁₅
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-43141 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 29, 2011