CY62157ESL Datasheet, PDF (1/12 Pages) Cypress Semiconductor – 8-Mbit (512K x 16) Static RAM

CY62157ESL MoBL^®
8-Mbit (512K x 16) Static RAM
Features
■ Very high speed: 45 ns
■ Wide voltage range: 2.2V–3.6V and 4.5V–5.5V
■ Ultra low standby power
❐ Typical Standby current: 2 μA
❐ Maximum Standby current: 8 μA
■ Ultra low active power
❐ Typical active current: 1.8 mA at f = 1 MHz
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Available in Pb-free 44-pin TSOP II package
Functional Description
The CY62157ESL is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL^®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Place the device
Logic Block Diagram
into standby mode when deselected (CE HIGH or both BHE and
BLE are HIGH). The input or output pins (IO₀ through IO₁₅) are
placed in a high impedance state when:
■ Deselected (CE HIGH)
■ Outputs are disabled (OE HIGH)
■ Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■ Write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO₀ through IO₇) is written into the location
specified on the address pins (A₀ through A₁₈). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO₈ through IO₁₅)
is written into the location specified on the address pins (A₀
through A₁₈).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO₀ to IO₇. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO₈ to IO₁₅. See the Truth Table on page 10 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Power Down
Circuit
A₁₀
A₉
A₈
A₇
A₆
A₅
A₄
A₃
A₂
A₁
A₀
CE
BHE
BLE
DATA IN DRIVERS
512K x 16
RAM Array
COLUMN DECODER
IO₀–IO₇
IO₈–IO₁₅
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-43141 Rev. **
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 04, 2008
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