CY62157DV30_10 Datasheet, PDF (1/15 Pages) Cypress Semiconductor – 8-Mbit (512K x 16) MoBL Static RAM

CY62157DV30 MoBL^®
8-Mbit (512K x 16) MoBL^ Static RAM
Features
■ Temperature ranges
❐ Industrial: –40 °C to 85 °C
■ Very high speed: 55 ns
■ Wide voltage range: 2.20 V–3.60 V
■ Pin-compatible with CY62157CV25, CY62157CV30, and
CY62157CV33
■ Ultra-low active power
❐ Typical active current: 1.5 mA @ f = 1 MHz
❐ Typical active current: 12 mA @ f = f_max
■ Ultra-low standby power
■ Easy memory expansion with CE₁, CE₂, and OE features
■ Automatic power-down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed/power
■ Available in Pb-free and non Pb-free 48-ball fine ball grid
array (FBGA), and Pb-free 44-pin thin small outline package
(TSOPII) package
Functional Description
The CY62157DV30 is a high-performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
Logic Block Diagram
A₁₀
A₉
AAA₈₇₆
A₅
A₄
A₃
A₂
AA₀₁
DATA-IN DRIVERS
512K × 16
RAM Array
COLUMN DECODER
Power-down
Circuit
This is ideal for providing More Battery Life (MoBL^®) in
portable applications such as cellular telephones.The device
also has an automatic power-down feature that significantly
reduces power consumption. The device can also be put into
standby mode when deselected (CE₁ HIGH or CE₂ LOW or
both BHE and BLE are HIGH). The input/output pins (I/O₀
through I/O₁₅) are placed in a high-impedance state when:
deselected (CE₁HIGH or CE₂ LOW), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH), or during a write operation (CE₁
LOW, CE₂ HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enables
(CE₁ LOW and CE₂ HIGH) and Write Enable (WE) input LOW.
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O₀
through I/O₇), is written into the location specified on the
address pins (A₀ through A₁₈). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O₈ through I/O₁₅) is written into
the location specified on the address pins (A₀ through A₁₈).
Reading from the device is accomplished by taking Chip
Enables (CE₁ LOW and CE₂ HIGH) and Output Enable (OE)
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O₀ to I/O₇. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O₈ to I/O₁₅. See the truth table for a complete description
of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
I/O₀–I/O₇
I/O₈–I/O₁₅
BHE
WE
OE
BLE
CE₂
CE₁
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-05392 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 25, 2010
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