CY62157DV18 Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 8M (512K x 16) Static RAM

CY62157DV18
MoBL2
Features
• Very high speed: 55 ns and 70 ns
• Voltage range: 1.65V to 1.95V
• Pin compatible with CY62157CV18
• Ultra-low active power
— Typical active current: 1 mA @ f = 1 MHz
— Typical active current: 10 mA @ f = f_MAX
• Ultra-low standby power
• Easy memory expansion with CE₁, CE₂, and OE
features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered in a 48-ball FBGA
Functional Description^[1]
The CY62157DV18 is a high-performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life (MoBL^®) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can be put into standby mode reducing
Logic Block Diagram
8M (512K x 16) Static RAM
power consumption by more than 99% when deselected Chip
Enable 1 (CE₁) HIGH or Chip Enable 2 (CE₂) LOW or both
BHE and BLE are HIGH. The input/output pins (I/O₀ through
I/O₁₅) are placed in a high-impedance state when: deselected
Chip Enable 1 (CE₁) HIGH or Chip Enable 2 (CE₂) LOW,
outputs are disabled (OE HIGH), both Byte High Enable and
Byte Low Enable are disabled (BHE, BLE HIGH) or during a
write operation (Chip Enable 1 (CE₁) LOW and Chip Enable 2
(CE₂) HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE₁) LOW and Chip Enable 2 (CE₂) HIGH and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O₀ through I/O₇), is written into the location
specified on the address pins (A₀ through A₁₈). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O₈ through
I/O₁₅) is written into the location specified on the address pins
(A₀ through A₁₈).
Reading from the device is accomplished by taking Chip
Enable 1 (CE₁) LOW and Chip Enable 2 (CE₂) HIGH and
Output Enable (OE) LOW while forcing the Write Enable (WE)
HIGH. If Byte Low Enable (BLE) is LOW, then data from the
memory location specified by the address pins will appear on
I/O₀ to I/O₇. If Byte High Enable (BHE) is LOW, then data from
memory will appear on I/O₈ to I/O₁₅. See the truth table at the
back of this data sheet for a complete description of read and
write modes.
DATA IN DRIVERS
A₁₀
A₉
A₈
A₇
A₆
512K x 16
A₅
RAM ARRAY
A₄
2048 x 256 x 16
A₃
A₂
A₁
A₀
I/O₀–I/O₇
I/O₈–I/O₁₅
COLUMN DECODER
Power - down
Circuit
BHE
BLE
BHE
WE
OE
BLE
CE₂
CE₁
CE₂
CE₁
Note:
1. For best practice recommendations, please refer to the Cypress application note System Design Guidelines on http://www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05126 Rev. *B
Revised March 17, 2003