CY62157CV25 Datasheet, PDF (1/13 Pages) Cypress Semiconductor – 512K x 16 Static RAM

CY62157CV25/30/33
MoBL™
512K x 16 Static RAM
Features
• High speed
— 55 ns and 70 ns availability
• Voltage range:
— CY62157CV25: 2.2V–2.7V
— CY62157CV30: 2.7V–3.3V
— CY62157CV33: 3.0V–3.6V
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 5.5 mA @ f = f_max (70 ns speed)
• Low standby power
• Easy memory expansion with CE₁, CE₂ and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The CY62157CV25/30/33 are high-performance CMOS static
RAMs organized as 512K words by 16 bits. These devices
feature advanced circuit design to provide ultra-low active cur-
rent. This is ideal for providing More Battery Life™ (MoBL™)
in portable applications such as cellular telephones. The de-
vices also have an automatic power-down feature that signifi-
cantly reduces power consumption by 80% when addresses
are not toggling. The device can also be put into standby mode
reducing power consumption by more than 99% when dese-
lected (CE₁ HIGH or CE₂ LOW or both BLE and BHE are
HIGH). The input/output pins (I/O₀ through I/O₁₅) are placed
in a high-impedance state when: deselected (CE₁ HIGH or
CE₂ LOW), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE₁ LOW and CE₂ HIGH and WE
LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE₁) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE₂) HIGH. If Byte Low Enable (BLE) is LOW, then data from
I/O pins (I/O₀ through I/O₇), is written into the location speci-
fied on the address pins (A₀ through A₁₈). If Byte High Enable
(BHE) is LOW, then data from I/O pins (I/O₈ through I/O₁₅) is
written into the location specified on the address pins (A₀
through A₁₈).
Reading from the device is accomplished by taking Chip
Enable 1 (CE₁) and Output Enable (OE) LOW and Chip Enable
2 (CE₂) HIGH while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins will appear on I/O₀ to
I/O₇. If Byte High Enable (BHE) is LOW, then data from mem-
ory will appear on I/O₈ to I/O₁₅. See the truth table at the back
of this data sheet for a complete description of read and write
modes.
The CY62157CV25/30/33 are available in a 48-ball FBGA
package.
Logic Block Diagram
DATA IN DRIVERS
A₁₀
A₉
A₈
A₇
A₆
512K × 16
A₅
RAM Array
A₄
2048 × 4096
A₃
A₂
A₁
A₀
I/O₀–I/O₇
I/O₈–I/O₁₅
COLUMN DECODER
Power -down
Circuit
BHE
BLE
BHE
WE
OE
BLE
CE₂
CE₁
CE₂
CE₁
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05014 Rev. *C
Revised April 23, 2002