CY62148V_02 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 4M (512K x 8) Static RAM

CY62148V MoBL^
4M (512K x 8) Static RAM
Features
• Wide voltage range: 2.7V–3.6V
• Ultra low active power
• Low standby power
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Package available in a 32 pin TSOPII and a 32-pin SOIC
package
Functional Description^[1]
The CY62148V is a high-performance CMOS static RAM
organized as 512K words by eight bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life (MoBL^) in
portable applications such as cellular telephones. The device
Logic Block Diagram
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can be put into standby mode when
deselected (CE HIGH).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O₀ through I/O₇) is then written into the location
specified on the address pins (A₀ through A₁₈).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O₀ through I/O₇) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW and WE LOW).
A₀
AA₁₂
AA₃₄
AA₅₆
AAA₇₈₉
CE
WE
OE
Data in Drivers
512K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O₀
I/O₁
I/O₂
I/O₃
I/O₄
I/O₅
I/O₆
I/O₇
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05070 Rev. *A
Revised August 27, 2002