CY62148E_13 Datasheet, PDF (1/17 Pages) Cypress Semiconductor – 4-Mbit (512 K x 8) Static RAM

CY62148E MoBL^®
4-Mbit (512 K × 8) Static RAM
4-Mbit (512 K × 8) Static RAM
Features
■ Very high speed: 45 ns
■ Voltage range: 4.5 V to 5.5 V
■ Pin compatible with CY62148B
■ Ultra low standby power
❐ Typical standby current: 1 µA
❐ Maximum standby current: 7 µA (Industrial)
■ Ultra low active power
❐ Typical active current: 2.0 mA at f = 1 MHz
■ Easy memory expansion with CE, and OE features
■ Automatic power-down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Available in Pb-free 32-pin thin small outline package (TSOP) II
and 32-pin small-outline integrated circuit (SOIC)^[1] packages
Functional Description
The CY62148E is a high performance CMOS static RAM
organized as 512 K words by 8-bits. This device features
Logic Block Diagram
advanced circuit design to provide ultra low standby current. This
is ideal for providing More Battery Life™ (MoBL^) in portable
applications. The device also has an automatic power-down
feature that significantly reduces power consumption when
addresses are not toggling. Placing the device into standby
mode reduces power consumption by more than 99% when
deselected (CE HIGH). The eight input and output pins (I/O₀
through I/O₇) are placed in a high impedance state when the
device is deselected (CE HIGH), Outputs are disabled (OE
HIGH), or during an active Write operation (CE LOW and WE
LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight I/O pins (I/O₀ through I/O₇)
is then written into the location specified on the address pins (A₀
through A₁₈).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the I/O pins.
The CY62148E device is suitable for interfacing with processors
that have TTL I/P levels. It is not suitable for processors that
require CMOS I/P levels. Please see Electrical Characteristics
on page 4 for more details and suggested alternatives.
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
CE
WE
OE
INPUT BUFFER
512K x 8
ARRAY
COLUMN DECODER
POWER
DOWN
I^IO^/O₀0
I^IO^/O₁1
I^IO^/O₂2
I^IO^/O₃3
I^IO^/O₄4
I^IO^/O₅5
I^IO^/O₆⁶
I^IO^/O₇⁷
Note
1. SOIC package is available only in 55 ns speed bin.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05442 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 6, 2013