CY62148EV30_12 Datasheet, PDF (1/18 Pages) Cypress Semiconductor – 4-Mbit (512 K × 8) Static RAM

CY62148EV30 MoBL^®
4-Mbit (512 K × 8) Static RAM
4-Mbit (512 K × 8) Static RAM
Features
■ Very high speed: 45 ns
❐ Wide voltage range: 2.20 V to 3.60 V
■ Temperature range:
❐ Industrial: –40 °C to +85 °C
❐ Automotive-A: –40 °C to +85 °C
■ Pin compatible with CY62148DV30
■ Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 7 A (Industrial)
■ Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Available in Pb-free 36-ball very fine-pitch ball grid array
(VFBGA), 32-pin thin small outline package (TSOP) II, and
32-pin small outline integrated circuit (SOIC) ^[1] packages
Functional Description
The CY62148EV30 is a high performance CMOS static RAM
organized as 512 K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL^) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Placing the device into standby mode reduces
power consumption by more than 99 percent when deselected
(CE HIGH). The eight input and output pins (I/O₀ through I/O₇)
are placed in a high impedance state when the device is
deselected (CE HIGH), the outputs are disabled (OE HIGH), or
during a write operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight I/O pins (I/O₀ through I/O₇)
is then written into the location specified on the address pins (A₀
through A₁₈).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the I/O pins.
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
CE
WE
OE
INPUT BUFFER
512K x 8
ARRAY
COLUMN DECODER
POWER
DOWN
I/O₀
IO0
I/O₁
IO1
I/O₂
IO2
I/O₃
IO3
I/O₄
IO4
I/O₅
IO5
I/O₆
IO6
I/O₇
IO7
Note
1. SOIC package is available only in 55 ns speed bin.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05576 Rev. *O
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 4, 2012