CY62148B_06 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 4-Mbit (512K x 8) Static RAM

CY62148B MoBL™
Features
• High Speed: 70 ns
• 4.5V–5.5V operation
• Low active power
— Typical active current: 2.5 mA @ f = 1 MHz
— Typical active current: 12.5 mA @ f = f_max(70 ns)
• Low standby current
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• CMOS for optimum speed/power
• Available in standard 32-lead (450-mil) SOIC, 32-lead
TSOP II and 32-lead Reverse TSOP II packages
Functional Description
The CY62148B is a high-performance CMOS static RAM
organized as 512K words by 8 bits. Easy memory expansion
Logic Block Diagram
A₀
A₁
A₄
A₅
A₆
A₇
A₁₂
A₁₄
A₁₆
A₁₇
CE
WE
OE
INPUT BUFFER
512 K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
4-Mbit (512K x 8) Static RAM
is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and three-state drivers. This device
has an automatic power-down feature that reduces power
consumption by more than 99% when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O₀ through I/O₇) is then written into the location
specified on the address pins (A₀ through A₁₈).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH for read. Under these conditions, the
contents of the memory location specified by the address pins
will appear on the I/O pins.
The eight input/output pins (I/O₀ through I/O₇) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY62148B is available in a standard 32-pin 450-mil-wide
body width SOIC, 32-pin TSOP II, and 32-pin Reverse TSOP
II packages.
I/O₀
I/O₁
I/O₂
I/O₃
I/O₄
I/O₅
I/O₆
I/O₇
Pin Configuration
Top View
SOIC
TSOP II
A₁₇ 1
A_{16 2}
A₁₄ 3
A_{12 4}
A₇ 5
A_{6 6}
A_{5 7}
A₄ 8
A_{3 9}
A_{2 10}
A_{1 11}
A₀ 12
I/O_{0 13}
I/O_{1 14}
I/O_{2 15}
GND ₁₆
32 V_CC
31 A₁₅
30 A₁₈
29 WE
28 _A13
27 _A8
26
25
A₉
A₁₁
24 _OE
23 A₁₀
22 CE
21 I/O7
20 ^I/O₆
19 ^I/O5
18 ^I/O4
17 I/O₃
GND
I/O₂
I/O₁
I/O₀
A₀
A₁
A₂
A₃
A₄
A₅
A₆
A₇
A₁₂
A₁₄
A₁₆
A₁₇
Top View
Reverse
TSOP II
16
17
15
18
14
19
13
20
12
21
11
22
10
23
9
24
8
25
7
26
6
27
5
28
4
29
3
30
2
31
1
32
I/O₃
I/O₄
I/O₅
I/O₆
I/O₇
CE
A₁₀
OE
A₁₁
A₉
A₈
A₁₃
WE
A₁₈
A₁₅
V_cc
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05039 Rev. *C
Revised August 2, 2006
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