CY62147G Datasheet, PDF (1/20 Pages) Cypress Semiconductor – 4-Mbit (256K words × 16 bit) Static RAM with Error-Correcting Code (ECC)

CY7C1041G
CY7C1041GE
4-Mbit (256K words × 16 bit) Static RAM
with Error-Correcting Code (ECC)
4-Mbit (256K words × 16 bit) Static RAM with Error-Correcting Code (ECC)
Features
■ High speed
❐ t_AA = 10 ns / 15 ns
■ Embedded ECC for single-bit error correction^[1]
■ Low active and standby currents
❐ Active current: I_CC = 38-mA typical
❐ Standby current: I_SB2 = 6-mA typical
■ Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and
4.5 V to 5.5 V
■ 1.0-V data retention
■ TTL-compatible inputs and outputs
■ Error indication (ERR) pin to indicate 1-bit error detection and
correction
■ Pb-free 44-pin SOJ, 44-pin TSOP II, and 48-ball VFBGA
packages
Functional Description
CY7C1041G and CY7C1041GE are high-performance CMOS
fast static RAM devices with embedded ECC. Both devices are
offered in single and dual chip-enable options and in multiple pin
configurations. The CY7C1041GE device includes an ERR pin
that signals an error-detection and correction event during a read
cycle.
Data writes are performed by asserting the Chip Enable (CE) and
Write Enable (WE) inputs LOW, while providing the data on I/O₀
through I/O₁₅ and address on A₀ through A₁₇ pins. The Byte High
Enable (BHE) and Byte Low Enable (BLE) inputs control write
operations to the upper and lower bytes of the specified memory
location. BHE controls I/O₈ through I/O₁₅ and BLE controls I/O₀
through I/O₇.
Data reads are performed by asserting the Chip Enable (CE) and
Output Enable (OE) inputs LOW and providing the required
address on the address lines. Read data is accessible on the I/O
lines (I/O₀ through I/O₁₅). Byte accesses can be performed by
asserting the required byte enable signal (BHE or BLE) to read
either the upper byte or the lower byte of data from the specified
address location.
All I/Os (I/O₀ through I/O₁₅) are placed in a high-impedance state
during the following events:
■ The device is deselected (CE HIGH)
■ The control signals (OE, BLE, BHE) are de-asserted
On the CY7C1041GE devices, the detection and correction of a
single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = HIGH)^[1]. See the Truth
Table on page 14 for a complete description of read and write
modes.
The logic block diagram is on page 2.
Product Portfolio
Product ^[2]
Features and Options (see Pin
Configurations on page 4)
CY7C1041G(E)18 Single or Dual Chip Enables
CY7C1041G(E)30 _{Optional ERR pins}
CY7C1041G(E)
Range
Industrial
V_CC
Range
(V)
1.65 V–2.2 V
2.2 V–3.6 V
4.5 V–5.5 V
Speed
(ns)
10/15
15
10
10
Power Dissipation
Operating I_CC, (mA)
f = f_max
Typ ^[3]
Max
Standby,
(mA)
I_SB2
Typ ^[3] Max
–
40
6
8
38
45
38
45
Notes
1. This device does not support automatic write-back on error detection.
2. The ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer Ordering Information on page 15 for details.
3. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V_CC = 1.8 V (for a V_CC range of 1.65 V–2.2 V),
V_CC = 3 V (for a V_CC range of 2.2 V–3.6 V), and V_CC = 5 V (for a V_CC range of 4.5 V–5.5 V), T_A = 25 °C.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-91368 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 2, 2016