CY62147EV30_11 Datasheet, PDF (1/16 Pages) Cypress Semiconductor – 4-Mbit (256K x 16) Static RAM Wide voltage range: 2.20 V to 3.60 V

CY62147EV30 MoBL^®
4-Mbit (256K x 16) Static RAM
Features
■ Very high speed: 45 ns
■ Temperature ranges
❐ Industrial: –40 °C to +85 °C
■ Wide voltage range: 2.20 V to 3.60 V
■ Pin compatible with CY62147DV30
■ Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 7 A (Industrial)
■ Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■ Easy memory expansion with CE ^[1] and OE features
■ Automatic power-down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Available in Pb-free 48-ball very fine ball grid array (VFBGA)
(single/dual CE option) and 44-pin thin small outline package
(TSOP) II packages
■ Byte power-down feature
Functional Description
The CY62147EV30 is a high performance CMOS static RAM
(SRAM) organized as 256K words by 16 bits. This device
features advanced circuit design to provide ultra low active
current. It is ideal for providing More Battery Life™ (MoBL^) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99 percent when deselected (CE
HIGH or both BLE and BHE are HIGH). The input and output pins
(I/O₀ through I/O₁₅) are placed in a high impedance state when:
■ Deselected (CE HIGH)
■ Outputs are disabled (OE HIGH)
■ Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■ Write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O₀ through I/O₇) is written into the location
specified on the address pins (A₀ through A₁₇). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O₈ through
I/O₁₅) is written into the location specified on the address pins
(A₀ through A₁₇).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O₀ to I/O₇. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O₈ to I/O₁₅. See the Truth Table on page 10 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
A₁₀
A₉
A₈
AAA₆₅₇
A₄
A₃
A₂
A₁
A₀
DATA IN DRIVERS
256K x 16
RAM Array
I/O₀–I/O₇
I/O₈–I/O₁₅
POWER DOWN
CIRCUIT
CE
BHE
BLE
COLUMN DECODER
BHE
CWEE^[1]
OE
BLE
Note
1.
BGA packaged device is
CE₂ such that when CE₁
offered in single CE and dual CE options. In this data sheet, for a dual CE
is LOW and CE₂ is HIGH, CE is LOW. For all other cases CE is HIGH.
device,
CE
refers
to
the
internal
logical
combination
of
CE₁
and
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05440 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 31, 2011
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