CY62147EV18_10 Datasheet, PDF (1/16 Pages) Cypress Semiconductor – 4-Mbit (256K x 16) Static RAM

CY62147EV18 MoBL^®
4-Mbit (256K x 16) Static RAM
Features
■ Very high speed: 55 ns
■ Wide voltage range: 1.65 V to 2.25 V
■ Pin compatible with CY62147DV18
■ Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 7 A
■ Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■ Ultra low standby power
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Available in a Pb-free 48-ball very fine ball grid array (VFBGA)
package
Functional Description
The CY62147EV18 is a high performance CMOS static RAM
organized as 256 K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL^) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99% when deselected (CE HIGH or both BLE and BHE are
HIGH). The input and output pins (I/O₀ through I/O₁₅) are placed
in a high impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), both the Byte High
Enable and the Byte Low Enable are disabled (BHE, BLE HIGH),
or during an active write operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW then data
from I/O pins (I/O₀ through I/O₇) is written into the location
specified on the address pins (A₀ through A₁₇). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O₈ through
I/O₁₅) is written into the location specified on the address pins
(A₀ through A₁₇).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O₀ to I/O₇. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O₈ to I/O₁₅. See the “Truth Table” on page 10 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
POWER DOWN
CIRCUIT
DATA IN DRIVERS
A₁₀
A₉
A₈
A₇
AA₆₅
256K x 16
A₄
RAM Array
A₃
A₂
A₁
A₀
COLUMN DECODER
CE
BHE
BLE
I/O₀–I/O₇
I/O₈–I/O₁₅
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-05441 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 06, 2010
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