CY62146E_13 Datasheet, PDF (1/16 Pages) Cypress Semiconductor – 4-Mbit (256 K x 16) Static RAM

CY62146E MoBL^®
4-Mbit (256 K × 16) Static RAM
4-Mbit (256 K × 16) Static RAM
Features
■ Very high speed: 45 ns
■ Wide voltage range: 4.5 V to 5.5 V
■ Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 7 A
■ Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Available in Pb-free 44-pin thin small outline package (TSOP)
Type II package
Functional Description
The CY62146E is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. It is
ideal for providing More Battery Life (MoBL^®) in portable
applications. The device also has an automatic power down
feature that reduces power consumption when addresses are
not toggling. Placing the device into standby mode reduces
power consumption by more than 99% when deselected (CE
HIGH). The input and output pins (I/O₀ through I/O₁₅) are placed
in a high impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or
during a write operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O₀ through I/O₇) is written into the location
specified on the address pins (A₀ through A₁₇). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O₈ through
I/O₁₅) is written into the location specified on the address pins
(A₀ through A₁₇).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O₀ to I/O₇. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O₈ to I/O₁₅. See Truth Table on page 11 for a
complete description of read and write modes.
The CY62146E device is suitable for interfacing with processors
that have TTL I/P levels. It is not suitable for processors that
require CMOS I/P levels. Please Electrical Characteristics on
page 4 for more details and suggested alternatives.
Logic Block Diagram
DATA IN DRIVERS
A₁₀
A₉
A₈
A₇
A₆
256 K × 16
A₅
A₄
RAM Array
A₃
A₂
A₁
A₀
COLUMN DECODER
I/O₀–I/O₇
I/O₈–I/O₁₅
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-07970 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 4, 2013