CY62146EV30_09 Datasheet, PDF (1/13 Pages) Cypress Semiconductor – 4-Mbit (256K x 16) Static RAM

CY62146EV30 MoBL^®
4-Mbit (256K x 16) Static RAM
Features
■ Very High Speed: 45 ns
■ Temperature Ranges
❐ Industrial: –40°C to +85°C
❐ Automotive-A: –40°C to +85°C
■ Wide Voltage Range: 2.20V–3.60V
■ Pin Compatible with CY62146DV30
■ Ultra Low Standby Power
❐ Typical standby current: 1 μA
❐ Maximum standby current: 7 μA
■ Ultra Low Active Power
❐ Typical active current: 2 mA at f = 1 MHz
■ Easy Memory Expansion with CE and OE Features
■ Automatic Power Down when Deselected
■ CMOS for Optimum Speed and Power
■ Available in a Pb-free 48-ball VFBGA and 44-pin TSOP II
Packages
Functional Description
The CY62146EV30 is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features an
advanced circuit design designed to provide an ultra low active
current. Ultra low active current is ideal for providing More
Battery Life™ (MoBL^®) in portable applications such as cellular
telephones. The device also has an automatic power down
feature that significantly reduces power consumption by 80
percent when addresses are not toggling.The device can also be
put into standby mode reducing power consumption by more
than 99 percent when deselected (CE HIGH). The input and
output pins (I/O₀ through I/O₁₅) are placed in a high impedance
state when: the device is deselected (CE HIGH), outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH), or a write operation is in
progress (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE ) and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O₀ through I/O₇) is written into the location
specified on the address pins (A₀ through A₁₇). If Byte High
Enable (BHE) is LOW, then data from the I/O pins (I/O₈ through
I/O₁₅) is written into the location specified on the address pins
(A₀ through A₁₇).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O₀ to I/O₇. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O₈ to I/O₁₅. See the “Truth Table” on page 9 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
A₁₀
A₉
A₈
A₇
A₆
A₅
A₄
A₃
A₂
A₁
A₀
DATA IN DRIVERS
256K x 16
RAM Array
IO₀–IO₇
IO₈–IO₁₅
COLUMN DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05567 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 23, 2009
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