CY62146E Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 4-Mbit (256K x 16) Static RAM

CY62146E MoBL^®
4-Mbit (256K x 16) Static RAM
Features
• Very high speed: 45 ns
• Wide voltage range: 4.5V–5.5V
• Ultra low standby power
— Typical standby current: 1 µA
— Maximum standby current: 7 µA
• Ultra low active power
— Typical active current: 2 mA @ f = 1 MHz
• Easy memory expansion with CE and OE features
• Automatic power down when deselected
• CMOS for optimum speed and power
• Offered in Pb-free 44-pin TSOP II package
Functional Description^[1]
The CY62146E is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL^®) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that reduces power
consumption when addresses are not toggling. Placing the
Logic Block Diagram
device into standby mode reduces power consumption by
more than 99% when deselected (CE HIGH). The input and
output pins (IO₀ through IO₁₅) are placed in a high impedance
state when:
• Deselected (CE HIGH)
• Outputs are disabled (OE HIGH)
• Both byte high enable and byte low enable are disabled
(BHE, BLE HIGH)
• When the write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO₀ through IO₇) is written into the location
specified on the address pins (A₀ through A₁₇). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO₈ through
IO₁₅) is written into the location specified on the address pins
(A₀ through A₁₇).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
If Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on IO₀ to IO₇.
If Byte High Enable (BHE) is LOW, then data from memory
appears on IO₈ to IO₁₅. See the “Truth Table” on page 9 for a
complete description of read and write modes.
DATA IN DRIVERS
A₁₀
A₉
A₈
A₇
A₆
256K x 16
A₅
A₄
RAM Array
A₃
A₂
A₁
A₀
COLUMN DECODER
IO₀–IO₇
IO₈–IO₁₅
BHE
WE
CE
OE
BLE
Note
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation
Document #: 001-07970 Rev. *C
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised May 4, 2007
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