CY62146CV18 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – 256K x 16 Static RAM

CY62146CV18 MoBL2™
256K x 16 Static RAM
Features
• High Speed
— 55 ns and 70 ns availability
• Low voltage range:
— 1.65V–1.95V
• Pin Compatible with CY62146BV18
• Ultra-low active power
— Typical Active Current: 0.5 mA @ f = 1 MHz
— Typical Active Current: 2 mA @ f = f_max (70 ns speed)
• Low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The CY62146CV18 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. These devices feature
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL™) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
Logic Block Diagram
reduces power consumption by 99% when addresses are not
toggling. The device can also be put into standby mode when
deselected (CE HIGH). The input/output pins (I/O₀ through
I/O₁₅) are placed in a high-impedance state when deselected
(CE HIGH), outputs are disabled (OE HIGH), BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O₀ through I/O₇), is
written into the location specified on the address pins (A₀
through A₁₆). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O₈ through I/O₁₅) is written into the location
specified on the address pins (A₀ through A₁₇).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O₀ to I/O₇. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O₈ to I/O₁₅. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The CY62146CV18 is available in a 48-Ball FBGA package.
DATA IN DRIVERS
A₉
A₈
A₇
A₆
A₅
256K x 16
A₄
RAM Array
A₃
2048 x 2048
A₂
A₁
A₀
COLUMN DECODER
I/O₀–I/O₇
I/O₈–I/O₁₅
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05010 Rev. *C
Revised August 28, 2002