CY62138V_06 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 2-Mbit (256K x 8) Static RAM

CY62138V MoBL™
2-Mbit (256K x 8) Static RAM
Features
• High Speed:
— 70 ns
• Low voltage range:
— 2.7V – 3.6V
• Ultra-low active power
• Low standby power
• Easy memory expansion with CS₁/CS₂ and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in non Pb-free 36-ball FBGA package
Functional Description
The CY62138V is a high-performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL^®) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that reduces power
consumption by 99% when addresses are not toggling. The
device can be put into standby mode when deselected (CS₁
HIGH or CS₂ LOW).
Writing to the device is accomplished by taking Chip Enable
One (CS₁) and Write Enable (WE) inputs LOW and Chip
Enable Two (CS₂) HIGH. Data on the eight I/O pins (I/O₀
through I/O₇) is then written into the location specified on the
address pins (A₀ through A₁₇).
Reading from the device is accomplished by taking Chip
Enable One (CS₁) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CS₂) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O₀ through I/O₇) are placed in a
high-impedance state when the device is deselected (CS₁
HIGH or CS₂ LOW), the outputs are disabled (OE HIGH), or
during a write operation (CS₁ LOW, CS₂ HIGH, and WE LOW).
The CY62138V is available in a 36-ball FBGA package.
Logic Block Diagram
A₀
A₁
A₂
A_A34
A5
A₆
A₇
A₈
C^CS^S₂₁
WE
OE
Data in Drivers
256K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
Pin Configuration
36-ball FBGA
TOP View
1
2
34
5
6
A 0 A₁ CS₂ ^A₃ ^A6 A₈
A
I/O_{4 A2} WE A₄ A₇ I/O₀
B
I/O₀
I/O₁
I/O₅
NC A₅
I/O₁
C
I/O₂
V_SS
V_CC
D
I/O₃
V_CC
V_SS
E
I/O₄
I/O₅
I/O₆
NC A₁₇
I/O₂
F
I/O₆
I/O₇ OE ^CS1 A₁₆ A₁₅ I/O₃
G
I/O₇
A₉
A₁₀ A₁₁ A₁₂ A₁₃ A₁₄
H
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05088 Rev. *B
Revised July 21, 2006
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