CY62138F_13 Datasheet, PDF (1/16 Pages) Cypress Semiconductor – 2-Mbit (256 K x 8) Static RAM

CY62138F MoBL^®
2-Mbit (256 K × 8) Static RAM
2-Mbit (256 K × 8) Static RAM
Features
■ High speed: 45 ns
■ Wide voltage range: 4.5 V to 5.5 V
■ Pin compatible with CY62138V
■ Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 5 A
■ Ultra low active power
❐ Typical active current: 1.6 mA @ f = 1 MHz
■ Easy memory expansion with CE₁, CE_2, and OE features
■ Automatic power down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Available in Pb-free 32-pin SOIC and 32-pin thin small outline
package (TSOP) II packages
Logic Block Diagram
Functional Description
The CY62138F is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL^®) in portable
applications. The device also has an automatic power down
feature that significantly reduces power consumption when
addresses are not toggling. Placing the device into standby
mode reduces power consumption by more than 99% when
deselected (CE₁ HIGH or CE₂ LOW).
To write to the device, take Chip Enable (CE₁ LOW and CE₂
HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O₀ through I/O₇) is then written into the location specified
on the address pins (A₀ through A₁₇).
To read from the device, take Chip Enable (CE₁ LOW and CE₂
HIGH) and output enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
The eight input and output pins (I/O₀ through I/O₇) are placed in
a high impedance state when the device is deselected (CE₁
HIGH or CE₂ LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE₁ LOW and CE₂ HIGH and WE
LOW).
The CY62138F device is suitable for interfacing with processors
that have TTL I/P levels. It is not suitable for processors that
require CMOS I/P levels. Please see Electrical Characteristics
on page 4 for more details and suggested alternatives.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-13194 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 4, 2013