CY62138F Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 2-Mbit (256K x 8) Static RAM

CY62138F MoBL^®
2-Mbit (256K x 8) Static RAM
Features
• High speed: 45 ns
• Wide voltage range: 4.5 V – 5.5 V
• Pin compatible with CY62138V
• Ultra low standby power
— Typical standby current: 1 µA
— Maximum standby current: 5 µA
• Ultra low active power
— Typical active current: 1.6 mA @ f = 1 MHz
• Easy memory expansion with CE₁, CE_2, and OE features
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in Pb-free 32-pin SOIC and 32-pin TSOP II
packages
Logic Block Diagram
Functional Description ^[1]
The CY62138F is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL^®) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99% when deselected (CE₁ HIGH
or CE₂ LOW).
To write to the device, take Chip Enable (CE₁ LOW and CE₂
HIGH) and Write Enable (WE) inputs LOW. Data on the eight
IO pins (IO₀ through IO₇) is then written into the location
specified on the address pins (A₀ through A₁₇).
To read from the device, take Chip Enable (CE₁ LOW and CE₂
HIGH) and output enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins appear on
the IO pins.
The eight input and output pins (IO₀ through IO₇) are placed
in a high impedance state when the device is deselected (CE₁
HIGH or CE₂ LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE₁ LOW and CE₂ HIGH and WE
LOW).
DATA IN DRIVERS
A0
IO0
A1
A2
IO1
A3
A4
IO2
A5
256K x 8
A6
IO3
A7
ARRAY
A8
IO4
A9
A10
IO5
A11
IO6
CE1
CE2
WE
COLUMN DECODER
POWER
DOWN
IO7
OE
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-13194 Rev. *A
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised March 26, 2007
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