CY62138CV30 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – 2M (256K x 8) Static RAM

CY62138CV25/30/33 MoBL^®
CY62138CV MoBL^®
Features
• Very high speed: 55 ns and 70 ns
• Voltage range:
— CY62138CV25: 2.2V–2.7V
— CY62138CV30: 2.7V–3.3V
— CY62138CV33: 3.0V–3.6V
— CY62138CV: 2.7V–3.6V
• Pin-compatible with CY62138V
• Ultra low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 5.5 mA @ f = f_max (70-ns
speed)
• Low standby power
• Easy memory expansion with CE₁, CE₂, and OE
features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered in a 36-ball FBGA
Functional Description^[1]
The CY62138CV25/30/33 and CY62138CV are high-perfor-
mance CMOS static RAMs organized as 256K words by eight
Logic Block Diagram
2M (256K x 8) Static RAM
bits. This device features advanced circuit design to provide
ultra-low active current. This is ideal for providing More Battery
Life™ (MoBL^®) in portable applications. The device also has
an automatic power-down feature that significantly reduces
power consumption by 80% when addresses are not toggling.
The device can be put into standby mode reducing power
consumption by more than 99% when deselected (CE₁ HIGH
or CE₂ LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE₁) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE₂) HIGH. Data on the eight I/O pins (I/O₀ through I/O₇) is
then written into the location specified on the address pins (A₀
through A₁₇).
Reading from the device is accomplished by taking Chip
Enable 1 (CE₁) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable 2 (CE₂) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O₀ through I/O₇) are placed in a
high-impedance state when the device is deselected (CE₁
HIGH or CE₂ LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE₁ LOW, CE₂ HIGH and WE LOW).
See the truth table at the back of this data sheet for a complete
description of read and write modes.
AAA⁰²¹
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CE₁
CE₂
WE
OE
Data in Drivers
256K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O₀
I/O₁
I/O₂
I/O₃
I/O₄
I/O₅
I/O₆
I/O₇
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05200 Rev. *D
Revised September 20, 2002