CY62137V_06 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 2-Mbit (128K x 16) Static RAM

CY62137V MoBL^®
2-Mbit (128K x 16) Static RAM
Features
• High Speed
— 55 ns
• Temperature Ranges
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
• Wide voltage range: 2.7V – 3.6V
• Ultra-low active, standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in Pb-free and non Pb-free standard
44-pin TSOP Type II package
Functional Description^[1]
The CY62137V is a high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL^®) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that reduces power
consumption by 99% when addresses are not toggling. The
device can also be put into standby mode when deselected
(CE HIGH) or when CE is LOW and both BLE and BHE are
HIGH. The input/output pins (I/O₀ through I/O₁₅) are placed in
a high-impedance state when: deselected (CE HIGH), outputs
are disabled (OE HIGH), BHE and BLE are disabled (BHE,
BLE HIGH), or during a write operation (CE LOW, and WE
LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O₀ through I/O₇), is
written into the location specified on the address pins (A₀
through A₁₆). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O₈ through I/O₁₅) is written into the location
specified on the address pins (A₀ through A₁₆).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O₀ to I/O₇. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O₈ to I/O₁₅. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Logic Block Diagram
A₁₀ 10
A₉
A₈
A₇
A₆
A₅
A₄
A₃
A₂
A₁
A₀
DATA IN DRIVERS
128K x 16
RAM Array
I/O₀–I/O₇
I/O₈–I/O₁₅
COLUMN DECODER
Power -Down
Circuit
CE
BHE
BLE
BHE
WE
CE
OE
BLE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05051 Rev. *E
Revised July 19, 2006
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