CY62137FV30_11 Datasheet, PDF (1/16 Pages) Cypress Semiconductor – 2-Mbit (128K x 16) Static RAM

CY62137FV30 MoBL^®
2-Mbit (128K x 16) Static RAM
Features
■ Very high speed: 45 ns
■ Temperature ranges
❐ Industrial: –40 °C to +85 °C
■ Wide voltage range: 2.20 V–3.60 V
■ Pin compatible with CY62137CV/CV25/CV30/CV33,
CY62137V, and CY62137EV30
■ Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 5 A (Industrial)
■ Ultra low active power
❐ Typical active current: 1.6 mA at f = 1 MHz (45 ns speed)
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Byte power down feature
■ Available in Pb free 48-Ball very fine ball grid array (VFBGA)
and 44-pin thin small outline package (TSOP) II package
Functional Description
The CY62137FV30 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL^®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99% when deselected (CE HIGH or both BLE and BHE are
HIGH). The input and output pins (I/O₀ through I/O₁₅) are placed
in a high impedance state in the following conditions when the
device is deselected (CE HIGH), the outputs are disabled (OE
HIGH), both the Byte High Enable and the Byte Low Enable are
disabled (BHE, BLE HIGH), or during an active write operation
(CE LOW and WE LOW).
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O₀ through I/O₇) is written into the location
specified on the address pins (A₀ through A₁₆). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O₈ through
I/O₁₅) is written into the location specified on the address pins
(A₀ through A₁₆).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW, while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O₀ to I/O₇. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O₈ to I/O₁₅. See the “Truth Table” on page 11 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
A₁₀
A₉
A₈
A₇
AA₆₅
A₄
A₃
A₂
A₁
A₀
DATA IN DRIVERS
128K x 16
RAM Array
I/O₀–I/O₇
I/O₈–I/O₁₅
COLUMN DECODER
BHE
WE
POWER DOWN
CE
CE
CIRCUIT
BHE
OE
BLE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-07141 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 03, 2011
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