CY62137FV18 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 2-Mbit (128K x 16) Static RAM

CY62137FV18 MoBL^®
2-Mbit (128K x 16) Static RAM
Features
■ Very high speed: 55 ns
■ Wide voltage range: 1.65V–2.25V
■ Pin compatible with CY62137CV18
■ Ultra low standby power
❐ Typical standby current: 1 µA
❐ Maximum standby current: 5 µA
■ Ultra low active power
❐ Typical active current: 1.6 mA @ f = 1 MHz
■ Ultra low standby power
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Byte power down feature
■ Available in a Pb-free 48-Ball VFBGA package
Functional Description
The CY62137FV18 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL^®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
Logic Block Diagram
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99% when deselected (CE HIGH or both BLE and BHE are
HIGH). The input and output pins (IO₀ through IO₁₅) are placed
in a high impedance state when:
■ Deselected (CE HIGH)
■ Outputs are disabled (OE HIGH)
■ Both the Byte High Enable and the Byte Low Enable are
disabled (BHE, BLE HIGH)
■ Write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO₀ through IO₇) is written into the location
specified on the address pins (A₀ through A₁₆). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO₈ through IO₁₅)
is written into the location specified on the address pins (A₀
through A₁₆).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO₀ to IO₇. If
Byte High Enable (BHE) is LOW, then data from the memory
appears on IO₈ to IO₁₅. See the “Truth Table” on page 9 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
DATA IN DRIVERS
A₁₀
A₉
A₈
A₇
A₆
128K x 16
A₅
A₄
RAM Array
A₃
A₂
A₁
A₀
IO₀–IO₇
IO₈–IO₁₅
COLUMN DECODER
BHE
POWER DOWN
CE
WE
CIRCUIT
BHE
CE
OE
BLE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-08030 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 01, 2007