CY62136CV30 Datasheet, PDF (1/13 Pages) Cypress Semiconductor – 2M (128K x 16) Static RAM

CY62136CV30/33 MoBL^
CY62136CV MoBL^
2M (128K x 16) Static RAM
Features
• Very high speed: 55 ns and 70 ns
• Voltage range:
— CY62136CV30: 2.7V–3.3V
— CY62136CV33: 3.0V–3.6V
— CY62136CV: 2.7V–3.6V
• Pin-compatible with the CY62136V
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 5.5 mA @ f = f_max (70-ns
speed)
• Low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered in a 48-ball FBGA
Functional Description^[1]
The and CY62136CV are high-performance CMOS static
RAM organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL^®) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 80% when addresses are not
toggling. The device can also be put into standby mode
reducing power consumption by more than 99% when
deselected (CE HIGH). The input/output pins (I/O₀ through
I/O₁₅) are placed in a high-impedance state when: deselected
(CE HIGH), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O₀ through I/O₇), is
written into the location specified on the address pins (A₀
through A₁₆). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O₈ through I/O₁₅) is written into the location
specified on the address pins (A₀ through A₁₆).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O₀ to I/O₇. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O₈ to I/O₁₅. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Logic Block Diagram
DATA IN DRIVERS
A₁₀
A₉
A₈
A₇
A₆
A₅
128K x 16
A₄
RAM Array
A₃
2048 x 1024
A₂
A₁
A₀
I/O₀–I/O₇
I/O₈–I/O₁₅
COLUMN DECODER
BHE
WE
CE
OE
BLE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05199 Rev. *D
Revised September 20, 2002