CY62128E_13 Datasheet, PDF (1/19 Pages) Cypress Semiconductor – 1-Mbit (128 K x 8) Static RAM

CY62128E MoBL^®
1-Mbit (128 K × 8) Static RAM
1-Mbit (128 K × 8) Static RAM
Features
■ Very high speed: 45 ns
■ Temperature ranges
❐ Industrial: –40 °C to +85 °C
❐ Automotive-A: –40 °C to +85 °C
❐ Automotive-E: –40 °C to +125 °C
■ Voltage range: 4.5 V to 5.5 V
■ Pin compatible with CY62128B
■ Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 4 A (Industrial)
■ Ultra low active power
❐ Typical active current: 1.3 mA at f = 1 MHz
■ Easy memory expansion with CE₁, CE_2, and OE features
■ Automatic power down when deselected
■ complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Offered in standard Pb-free 32-pin STSOP, 32-pin SOIC, and
32-pin thin small outline package (TSOP) Type I packages
Logic Block Diagram
Functional Description
The CY62128E is a high performance CMOS static RAM
organized as 128K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL^) in portable
applications. The device also has an automatic power down
feature that significantly reduces power consumption when
addresses are not toggling. Placing the device into standby
mode reduces power consumption by more than 99 percent
when deselected (CE₁ HIGH or CE₂ LOW). The eight input and
output pins (I/O₀ through I/O₇) are placed in a high impedance
state when the device is deselected (CE₁ HIGH or CE₂ LOW),
the outputs are disabled (OE HIGH), or a write operation is in
progress (CE₁ LOW and CE₂ HIGH and WE LOW)
To write to the device, take Chip Enable (CE₁ LOW and CE₂
HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O₀ through I/O₇) is then written into the location specified
on the address pins (A₀ through A₁₆).
To read from the device, take Chip Enable (CE₁ LOW and CE₂
HIGH) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
The CY62128E device is suitable for interfacing with processors
that have TTL I/P levels. It is not suitable for processors that
require CMOS I/P levels. Please see Electrical Characteristics
on page 5 for more details and suggested alternatives.
CE1
CE2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
WE
OE
INPUT BUFFER
128K x 8
ARRAY
COLUMN DECODER
POWER
DOWN
I_I/_/O_O00
I_I/_/O_O11
II//OO₂₂
II//OO₃₃
II//OO₄
II//OO₅
I^I/^/O^O₆
I^I/^/O^O₇7
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05485 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 3, 2013