CY62128DV30 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 1 Mb (128K x 8) Static RAM

CY62128DV30
MoBL^
Features
• Very high speed: 55 and 70 ns
• Wide voltage range: 2.2V to 3.6V
• Pin compatible with CY62128V
• Ultra-low active power
— Typical active current: 0.85 mA @ f = 1 MHz
— Typical active current: 5 mA @ f = f_MAX
• Ultra-low standby power
• Easy memory expansion with CE₁, CE₂, and OE
features
• Automatic power-down when deselected
• Packages offered in a 32-lead SOIC, a 32-lead TSOP, a
32-lead Short TSOP, and a 32-lead Reverse TSOP
Functional Description^[1]
The CY62128DV30 is a high-performance CMOS static RAM
organized as 128K words by 8 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life (MoBL^®) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
Logic Block Diagram
1 Mb (128K x 8) Static RAM
power consumption by 90% when addresses are not toggling.
The device can be put into standby mode reducing power con-
sumption by more than 99% when deselected Chip Enable 1
(CE₁) HIGH or Chip Enable 2 (CE₂) LOW. The input/output
pins (I/O₀ through I/O₇) are placed in a high-impedance state
when: deselected Chip Enable 1 (CE₁) HIGH or Chip Enable
2 (CE₂) LOW, outputs are disabled (OE HIGH), or during a
write operation (Chip Enable 1 (CE₁) LOW and Chip Enable 2
(CE₂) HIGH and Write Enable (WE) LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE₁) LOW with Chip Enable 2 (CE₂) HIGH and Write En-
able(WE) LOW. Data on the eight I/O pins is then written into
the location specified on the Address pin (A₀ thro. A₁₆).
Reading from the device is accomplished by taking Chip En-
able 1 (CE₁) LOW with Chip Enable 2 (CE₂) HIGH and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O_o through I/O₇) are placed in a
high-impedance state when the device is deselected (CE₁
HIGH or CE₂ LOW), the outputs are disabled (OE HIGH) or
during a write operation (CE₁ LOW, CE₂ HIGH), and WE
LOW).
Data in Drivers
A0
A1
A2
A3
A4
A5
A6
A7
AAA1098
A11
128K x 8
ARRAY
CE₁
CE₂
WE
OE
COLUMN
DECODER
Power-
down
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation •
Document #: 38-05231 Rev. *C
3901 North First Street • San Jose, CA 95134 • 408-943-2600
Revised August 29, 2003