CY62128BN_09 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – 1-Mbit (128K x 8) Static RAM

CY62128BN
MoBL^®
1-Mbit (128K x 8) Static RAM
Features
• Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
• 4.5V–5.5V operation
• CMOS for optimum speed/power
• Low active power
(70 ns Commercial, Industrial, Automotive-A)
— 82.5 mW (max.) (15 mA)
• Low standby power
(55/70 ns Commercial, Industrial, Automotive-A)
— 110 µW (max.) (15 µA)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE₁, CE₂, and OE options
• Available in Pb-free and non-Pb-free 32-pin (450
mil-wide) SOIC, 32-pin STSOP and 32-pin TSOP-I
Functional Description^[1]
The CY62128BN is a high-performance CMOS static RAM
organized as 128K words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE₁), an active
HIGH Chip Enable (CE₂), an active LOW Output Enable (OE),
and tri-state drivers. This device has an automatic
power-down feature that reduces power consumption by more
than 75% when deselected.
Writing to the device is accomplished by taking Chip Enable
One (CE₁) and Write Enable (WE) inputs LOW and Chip
Enable Two (CE₂) input HIGH. Data on the eight I/O pins (I/O₀
through I/O₇) is then written into the location specified on the
address pins (A₀ through A₁₆).
Reading from the device is accomplished by taking Chip
Enable One (CE₁) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE₂) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O₀ through I/O₇) are placed in a
high-impedance state when the device is deselected (CE₁
HIGH or CE₂ LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE₁ LOW, CE₂ HIGH, and WE LOW).
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
CCEE12
WE
OE
INPUT BUFFER
128K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
Pin Configuration
Top View
SOIC
NC 1
32 V_CC
A16 2
31 A15
A14 3
30 _CE2
I/O ₀
A12 4
29 _WE
A7 ⁵
28 _A13
I/O ₁
A6 ⁶
27 _A8
A5 7
26 _A9
I/O ₂
A4 ⁸
25 _A11
A3 ⁹
24 _OE
I/O ₃
A2 ¹⁰
23 _A10
A1 11
22 CE1
I/O ₄
A0 ¹²
21 I/O7
I/O0 13
20 I/O6
I/O ₅
I/O1 ¹⁴
19 I/O5
I/O2 15
18 I/O4
I/O ₆
G^GgGNnNcD 16
17 I/O3
I/O ₇
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-06498 Rev. *A
Revised August 3, 2006
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