CY62127BV Datasheet, PDF(1/11 Page) Cypress Semiconductor

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CY62127BV Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 64K x 16 Static RAM

27B V

CY62127BV

64K x 16 Static RAM

Features

â¢ 2.7Vâ3.6V operation

â¢ CMOS for optimum speed/power

â¢ Low active power (70 ns, LL version)

â 54 mW (max.) (15 mA)

â¢ Low standby power (70 ns, LL version)

â 54 ÂµW (max.) (15 ÂµA)

â¢ Automatic power-down when deselected

â Power down either with CE or BHE and BLE HIGH

â¢ Independent control of Upper and Lower Bytes

â¢ Available in 44-pin TSOP II (forward) and fBGA

Functional Description

The CY62127BV is a high-performance CMOS Static RAM

organized as 65,536 words by 16 bits. This device has an au-

tomatic power-down feature that significantly reduces power

consumption by 99% when deselected. The device enters

power-down mode when CE is HIGH or when CE is LOW and

both BLE and BHE are HIGH.

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is

written into the location specified on the address pins (A0

through A15). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O9 through I/O16) is written into the location

specified on the address pins (A0 through A15).

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is

LOW, then data from memory will appear on I/O9 to I/O16. See

the truth table at the back of this data sheet for a complete

description of read and write modes.

The input/output pins (I/O1 through I/O16) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), the BHE and BLE

are disabled (BHE, BLE HIGH), or during a write operation (CE

LOW, and WE LOW).

The CY62127BV is available in standard 44-pin TSOP Type II

(forward pinout) and fBGA packages.

Logic Block Diagram

DATA IN DRIVERS

A12

A11

A10

64K x 16

RAM Array

1024 X 1024

COLUMN DECODER

I/O1âI/O8

I/O9âI/O16

BHE

BLE

Pin Configurations

TSOP II (Forward)

Top View

A4 1

A3 2

A2 3

A1 4

A0 5

CE 6

I/O1 7

I/O2 8

I/O3 9

I/O4 10

VCC 11

VSS 12

I/O5 13

I/O6 14

I/O7 15

I/O8 16

WE 17

A15 18

A14 19

A13 20

A12 21

NC 22

44 A5

43 A6

42 A7

41 OE

40 BHE

39 BLE

38 I/O16

37 I/O15

36 I/O14

35 I/O13

34 VSS

33 VCC

32 I/O12

31 I/O11

30 I/O10

29 I/O9

28 NC

27 A8

26 A9

25 A10

24 A11

23 NC

Cypress Semiconductor Corporation â¢ 3901 North First Street â¢ San Jose â¢ CA 95134 â¢ 408-943-2600

Document #: 38-05155 Rev. **

Revised September 6, 2001

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