CY54FCT138T Datasheet, PDF (1/6 Pages) Cypress Semiconductor – 1-of-8 Decoder

1CY 54/7 4FCT138 T
fax id: 7013
CY54/74FCT138T
Features
• Function, pinout, and drive compatible with FCT and
F logic
• FCT-C speed at 5.0 ns max. (Com’l),
FCT-A speed at 5.8 ns max. (Com’l)
• Reduced V_OH (typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• ESD > 2000V
• Matched rise and fall times
• Fully compatible with TTL input and output logic levels
• Extended commercial range of −40°C to +85°C
• Sink current
64 mA (Com’l),
32 mA (Mil)
1-of-8 Decoder
Source current 32 mA (Com’l),
12 mA (Mil)
• Dual 1-of-8 decoder with enables
Functional Description
The FCT138T is a 1-of-8 decoder. The FCT138T accepts
three binary weighted inputs (A₀, A₁, A₂) and, when enabled,
provides eight mutually exclusive active LOW outputs
(O₀–O₇). The FCT138T features three enable inputs, two
active LOW (E₁, E₂) and one active HIGH (E₃).
All inputs will be HIGH unless E₁ and E₂ are LOW and E₃ is
HIGH. This multiple enable function allows easy parallel
expansion of the device to a 1-of-32 (5 lines to 32 lines)
decoder with just four FCT138T devices and one inverter.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Logic Block Diagram
A₂ A₁
A₀
E₁ E₂ E₃
O₇
O₆
O₅
O₄
O₃
O₂
O₁
O₀
FCT138T–1
Pin Configurations
LCC
Top View
8 7 654
O_{7 9}
3 ^A1
GND ₁₀
2 ^A0
NC 11
O₆ 12
1 ^NC
20 ^VCC
O₅ 13
19 O0
14 15 16 17 18
FCT138T–2
DIP/SOIC/QSOP
Top View
A₀ 1
A_{1 2}
A₂ 3
E₁ 4
E_{2 5}
E_{3 6}
O_{7 7}
GND ₈
16 VCC
15 O₀
14 O₁
13 O₂
12 O3
11 ^O4
10 O5
9 O6
FCT138T–3
Pin Description
Name
A
E₁−E₂
E₃
O
Description
Address Inputs
Enable Inputs (Active LOW)
Enable Input (Active HIGH)
Outputs
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
May 1994 – Revised March 17, 1997