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CY3130 Datasheet, PDF (1/7 Pages) Cypress Semiconductor – Warp Enterprise™ VHDL CPLD Software | |||
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CY3130
Warp Enterprise⢠VHDL CPLD Software
Features
⢠VHDL (IEEE 1076 and 1164) high-level language
compilers with the following features
â Designs are portable across multiple devices
and/or EDA environments
â Facilitates the use of industry-standard simulation
and synthesis tools for board- and system-level de-
sign
â Support for functions and libraries facilitating
modular design methodology
â Support for enumerated types, operator overload-
ing, For... Generate statements and Integers
⢠Several design entry methods support high-level and
low-level design descriptions
â Graphical HDL Block Diagram editor with a library of
blocks and a text-to-block conversion utility from
Aldec
â Aldec Active-HDL⢠FSM graphical Finite State
Machine editor
â Behavioral VHDL (IF...THEN...ELSE; CASE...)
â Boolean
â Structural VHDL
â Designs can include multiple entry methods (but
only one HDL) in a single design.
⢠Language Assistant library of VHDL templates
⢠Flow Manager Interface to keep track of complex
projects
⢠UltraGen⢠Synthesis and Fitting Technology
â Infers âmodulesâ such as adders, comparators, etc.,
from behavioral descriptions and replaces them with
circuits pre-optimized for the target device
â User-selectable speed and/or area optimization on a
block-by-block basis
â Perfectly integrated synthesis and fitting
â Automatic selection of optimal flip-flop type
(D type/T type)
â Automatic pin assignment
⢠Ability to specify timing constraints for all of the
Delta39K and PSI devices
⢠Support for all Cypress Programmable Logic Devices
â Programmable Serial Interface⢠(PSIâ¢)
â Delta39K⢠CPLDs
â Ultra37000⢠CPLDs
â FLASH370i⢠CPLDs
â MAX340⢠CPLDs
â Industry standard PLDs (16V8, 20V8, 22V10)
⢠VHDL or Verilog timing model output for use with
third-party simulators
⢠Timing simulation provided by Active-HDL⢠Sim
Release 4.1 from Aldec
â Graphical waveform simulator
â Graphical entry and modification of all waveforms
â Ability to compare waveforms and highlight differ-
ences before and after a design change
â Ability to probe internal nodes
â Display of inputs, outputs, and high-impedance (Z)
signals in different colors
â Automatic clock and pulse creation
â Support for buses
â Unlimited simulation time
⢠Architecture Explorer and Dynamic Timing Simulator
for PSI and Delta39K devices:
â Graphical representation of exactly how your design
will be implemented on your specific target device
â Zoom from the device level down to the macrocell
level
â Determine the timing for any path and view that path
on a graphical representation of the chip
⢠Static Timing Report for all devices
⢠Source-Level Behavioral Simulation and Debugger
from Aldec
⢠Testbench Generation
⢠C3ISR Programming Cable
⢠Delta39K\Ultra37000 prototype board with a CY37256V
160-pin TQFP device and a CY39100V 208-pin PQFP
device
⢠On-line documentation and help
Functional Description
Warp Enterprise⢠is an integration of the Warp Profes-
sional⢠CPLD Development package with additional sophis-
ticated EDA software features from Aldec. In addition to
accepting IEEE 1076/1164 VHDL text and graphical finite state
machines for design entry, Warp Enterprise VHDL provides a
graphical HDL block diagram editor with a library of graphical
HDL blocks pre-optimized for Cypress devices. Plus, it
provides a utility to convert HDL text into graphical HDL blocks.
Warp Enterprise synthesizes and optimizes the entered
design, and outputs a JEDEC or Intel® hex file for the desired
PLD or CPLD (see Figure 1). For simulation, Warp Enterprise
provides a timing simulator, a source-level behavioral
simulator, as well as VHDL and Verilog timing models for use
with third party simulators. Warp Enterprise also provides the
designer with important productivity tools such as a testbench
generation wizard and the Architecture Explorer graphical
analysis tool.
Cypress Semiconductor Corporation ⢠3901 North First Street ⢠San Jose, CA 95134 ⢠408-943-2600
Document #: 38-03050 Rev. *C
Revised August 18, 2003
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