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CY3128 Datasheet, PDF (1/8 Pages) Cypress Semiconductor – Warp Professional CPLD Software | |||
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CY3128
Warp Professional⢠CPLD Software
Features
⢠VHDL (IEEE 1076 and 1164) and Verilog (IEEE 1364)
high-level language compilers with the following fea-
tures:
â Designs are portable across multiple devices
and/or EDA environments
â Facilitates the use of industry-standard simulation
and synthesis tools for board- and system-level
design
â Support for functions and libraries facilitating
modular design methodology
⢠Support for all Cypress Programmable Logic Devices
â PSI⢠(Programmable Serial Interfaceâ¢)
â Delta39K⢠CPLDs
â Quantum38K⢠CPLDs
â Ultra37000⢠CPLDs
â FLASH370i⢠CPLDs
â MAX340⢠CPLDs
â Industry standard PLDs (16V8, 20V8, 22V10)
⢠VHDL and Verilog timing model output for use with
third-party simulators
⢠IEEE Standard 1076 and 1164 VHDL synthesis
supports:
⢠Active-HDL⢠Sim Release 4.1 timing simulation from
Aldec
â Enumerated types
â Graphical waveform simulator
â Operator overloading
â For... Generate statements
â Integers
⢠IEEE Standard 1364 Verilog synthesis supports:
â Reduction and conditional operators
â Blocking and non-blocking procedural assignments
â While loops
â Integers
⢠Several design entry methods support high-level and
low-level design descriptions:
â Graphical HDL Block Diagram editor and a library of
blocks from Aldec
â Aldec Active-HDL⢠FSM graphical Finite State
Machine editor
â Behavioral VHDL and Verilog (IF...THEN...ELSE;
CASE...)
â Boolean
â Structural Verilog and VHDL
â Graphical entry and modification of stimulus wave-
forms
â Ability to compare waveforms and highlight differ-
ences before and after a design change
â Ability to probe internal nodes
â Display of inputs, outputs, and high impedance (Z)
signals in different colors
â Automatic clock and pulse creation
â Support for buses
â Up to 5 ms simulation time
⢠Architecture Explorer analysis tool and Dynamic Tim-
ing Analysis for PSI, Delta39K and Quantum38K devic-
es:
â Graphical representation of exactly how your design
will be implemented on your specific target device
â Zoom from the device level down to the macrocell
level
â Determine the timing for any path and view that path
on a graphical representation of the chip
â Designs can include multiple entry methods (but
⢠Static Timing Report for all devices
only one HDL) in a single design.
⢠UltraISR Programming Cable
⢠Language Assistant library of VHDL and Verilog tem-
plates
⢠Flow Manager Interface to keep track of complex
⢠Delta39K\Ultra37000 prototype board with a CY37256V
160-pin TQFP device and a CY39100V 208-pin PQFP
device[1]
projects
⢠On-line documentation and help
⢠UltraGen⢠Synthesis and Fitting Technology:
â Infers âmodulesâ such as adders, comparators, etc.,
Functional Description
from behavioral descriptions and replaces them with Warp Professional⢠is an integration of the Warp® CPLD De-
circuits pre-optimized for the target device.
velopment package with additional sophisticated EDA soft-
â User-selectable speed and/or area optimization on a
block-by-block basis
â Perfectly integrated synthesis and fitting
â Automatic selection of optimal flip-flop type
(D type/T type)
ware features from Aldec. In addition to accepting IEEE
1076/1164 VHDL text, IEEE 1364 Verilog text and graphical
finite state machines for design entry, Warp Professional pro-
vides a graphical HDL block diagram editor with a library of
graphical HDL blocks pre-optimized for Cypress devices. It
synthesizes and optimizes the entered design, and outputs a
â Automatic pin assignment
JEDEC or Intel hex file for the desired PLD or CPLD (see Fig-
ure 1). For simulation, Warp Professional provides a timing
simulator, as well as VHDL timing models for use with third
party simulators. Warp Professional also provides the design-
er with important productivity tools like the Architecture Explor-
er graphical analysis tool.
Note:
1. Cypress reserves the right to substitute prototype boards based on availability.
Cypress Semiconductor Corporation ⢠3901 North First Street ⢠San Jose ⢠CA 95134 ⢠408-943-2600
Document #: 38-03047 Rev. *A
Revised January 9, 2002
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