CY3125 Datasheet, PDF (1/8 Pages) Cypress Semiconductor – Warp CPLD Development Tool for UNIX

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CY3125
Warp^® CPLD Development Tool for UNIX
Features
• VHDL (IEEE 1076 and 1164) and Verilog (IEEE 1364)
high-level language compilers with the following
features:
— Designs are portable across multiple devices
and/or EDA environments
— Facilitates the use of industry-standard simulation
and synthesis tools for board and system-level
design
— Support for functions and libraries facilitating
modular design methodology
• IEEE Standard 1076 and 1164 VHDL synthesis
supports:
— Enumerated types
— Operator overloading
— For... Generate statements
— Integers
• IEEE Standard 1364 Verilog synthesis supports:
— Reduction and conditional operators
— Blocking and non-blocking procedural assignments
— While loops
— Integers
• Several design entry methods support high-level and
low-level design descriptions:
— Behavioral VHDL and Verilog (IF...THEN...ELSE;
CASE...)
— Boolean
— Structural Verilog and VHDL
— Designs can include multiple entry methods (but
only one HDL language) in a single design.
• UltraGen™ Synthesis and Fitting Technology:
— Infers “modules” such as adders, comparators, etc.,
from behavioral descriptions and replaces them with
circuits pre-optimized for the target device.
— User-selectable speed and/or area optimization on a
block-by-block basis
— Perfect communication between synthesis and fit-
ting
— Automatic selection of optimal flip-flop type
(D type/T type)
— Automatic pin assignment
• Supports for the following Cypress Programmable
Logic Devices:
— PSI™ (Programmable Serial Interface™)
— Delta39K™ CPLDs
— Quantum38K™ CPLDs
— Ultra37000™ CPLDs
— FLASH370i™ CPLDs
— MAX340™ CPLDs
— Industry-standard PLDs (16V8, 20V8, 22V10)
• VHDL and Verilog timing model output for use with
third-party simulators
• Static Timing Report:
— Provides timing information for any path broken
down by the different steps of the path
• Architecture Explorer and Dynamic Timing Analysis for
PSI, Delta39K and Quantum38K devices:
— Graphical representation of exactly how your design
will be implemented on your specific target device
— Zoom from the device level down to the macrocell
level
— Determine the timing for any path and view that path
on a graphical representation of the chip
• Workstation support for Sun Solaris™
• On-line documentation and help
Functional Description
VHDL
Verilog
State Machine
UltraGen^TM
Synthesis
and
Fitting
Programming
File
Timing
Simulator
VHDL, Verilog
&Third-Party
Simulation Models
Figure 1. Warp^® VHDL Design Flow
Warp^® is a state-of-the-art HDL compiler for designing with
Cypress’s Complex Programmable Logic Devices (CPLDs).
Warp utilizes a subset of IEEE 1076/1164 VHDL and IEEE
1364 Verilog as its Hardware Description Languages (HDL) for
design entry. Then, it synthesizes and optimizes the entered
design, and outputs a JEDEC or Intel hex file for the desired
PLD or CPLD (see Figure 1). Furthermore, Warp accepts
VHDL or Verilog produced by the Active-HDL FSM graphical
Finite State Machine editor. For simulation, Warp provides a
timing simulator, as well as VHDL and Verilog timing models
for use with third party simulators.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-03046 Rev. *A
Revised January 9, 2002