CY3120 Datasheet, PDF (1/8 Pages) Cypress Semiconductor – Warp-R CPLD Development Software for PC

CY3120
Warp^ CPLD Development Software for PC
Features
• VHDL (IEEE 1076 and 1164) and Verilog (IEEE 1364)
high-level language compilers with the following
features
— Designs are portable across multiple devices
and/or EDA environments
— Facilitates the use of industry-standard simulation
and synthesis tools for board and system-level
design
— Support for functions and libraries facilitating
modular design methodology
• IEEE Standard 1076 and 1164 VHDL synthesis supports
— Enumerated types
— Operator overloading
— For... Generate statements
— Integers
• IEEE Standard 1364 Verilog synthesis supports
— Reduction and conditional operators
— Blocking and non-blocking procedural assignments
— While loops
— Integers
• Several design entry methods support high-level and
low-level design descriptions
— Behavioral VHDL and Verilog (IF...THEN...ELSE;
CASE...)
— Boolean
— Aldec Active-HDL™ FSM graphical Finite State
Machine editor
— Structural Verilog and VHDL
— Designs can include multiple entry methods (but
only one HDL language) in a single design
• UltraGen™ Synthesis and Fitting Technology
— Infers “modules” such as adders, comparators, etc.,
from behavioral descriptions and replaces them with
circuits pre-optimized for the target device
— User selectable speed and/or area optimization on a
block-by-block basis
— Perfect communication between synthesis and
fitting
— Automatic selection of optimal flip-flop type
(D type/T type)
— Automatic pin assignment
• Ability to specify timing constraints for all of the
Delta39K and PSI devices
• Supports all Cypress Programmable Logic Devices
— PSI™ (Programmable Serial Interface)
— Delta39K™ Complex Programmable Logic Devices
(CPLDs)
— Ultra37000™ CPLDs
— FLASH370i™ CPLDs
— MAX340™ CPLDs
— Industry standard PLDs (16V8, 20V8, 22V10)
• VHDL and Verilog timing model output for use with
third-party simulators
• Timing simulation provided by Active-HDL™ Sim
Release 3.3 from Aldec
— Graphical waveform simulator
— Entry and modification of on-screen waveforms
— Ability to probe internal nodes
— Display of inputs, outputs, and high impedance (Z)
signals in different colors
— Automatic clock and pulse creation
— Support for buses
• Architecture Explorer and Dynamic Timing Analysis for
PSI and Delta39K devices
— Graphical representation of exactly how your design
will be implemented on your specific target device
— Zoom from the device level down to the macrocell
level
— Determine the timing for any path and view that path
on a graphical representation of the chip
• Static Timing Report for all devices
• PC Support (Windows 98™, Windows NT™ 4.0, and
Windows XP™)
• On-line documentation and help
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-03049 Rev. *C
Revised August 18, 2002