CY2XP31_11 Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 312.5 MHz LVPECL Clock Generator

CY2XP31
312.5 MHz LVPECL Clock Generator
Features
■ One LVPECL output pair
■ Output frequency: 312.5 MHz
■ External crystal frequency: 25 MHz
■ Low RMS phase jitter at 312.5 MHz, using 25 MHz crystal
(1.875 MHz to 20 MHz): 0.3 ps (typical)
■ Pb-free 8-Pin TSSOP package
■ Supply voltage: 3.3 V or 2.5 V
■ Commercial and industrial temperature ranges
Logic Block Diagram
Functional Description
The CY2XP31 is a PLL (Phase Locked Loop) based high
performance clock generator. It is optimized to generate 10 Gb
Ethernet, SONET, and other high performance clock
frequencies. It also produces an output frequency that is 12.5
times the crystal frequency. It uses Cypress’s low noise VCO
technology to achieve less than 1 ps typical RMS phase jitter,
which meets both 10 Gb Ethernet and SONET jitter
requirements. The CY2XP31 has a crystal oscillator interface
input and one LVPECL output pair.
XIN
External
Crystal
CRYSTAL
OSCILLATOR
PHASE
DETECTOR
VCO
/2
XOUT
CLK
CLK#
OE
Pinouts
/25
Figure 1. Pin Diagram – 8-Pin TSSOP
VDD 1
VSS 2
XOUT 3
XIN 4
8
VDD
7
CLK
6
CLK#
5
OE
Table 1. Pin Definition – 8-Pin TSSOP
Pin Number Pin Name
I/O Type
1, 8
VDD
Power
2
VSS
Power
3, 4
XOUT, XIN
XTAL Output and Input
5
OE
CMOS Input
6,7
CLK#, CLK
LVPECL Output
Description
3.3 V or 2.5 V power supply. All supply current flows through pin 1
Ground
Parallel resonant crystal interface
Output enable. When HIGH, the output is enabled. When LOW, the
output is high impedance
Differential clock output
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-06385 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 7, 2011
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