CY2XP304 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – High-Frequency Programmable PECL Clock Generation Module

CY2XP304
High-Frequency Programmable PECL
Clock Generation Module
Features
• Period jitter peak-peak 125MHz(max.) = 55 ps
• Four low-skew LVPECL outputs
• Phase-locked loop (PLL) multiplier select
• Serially-configurable multiply ratios
• Eight-bit feedback counter and six-bit reference
counter for high accuracy
• HSTL inputs—HSTL-to-LVPECL level translation
• 125- to 500-MHz output range for high-speed
applications
• High-speed PLL bypass mode to 1.5 GHz
• 36-VFBGA, 6 × 8 × 1 mm
• 3.3V operation
Block Diagram
PLL_MULT
XIN
XOUT
SER CLK
SER DATA
INA
INAB
CLK_SEL
XTAL
0
PLL
OSCILLATOR
xM
1
CLK0
CLK0B
CLK1
CLK1B
CLK2
CLK2B
CLK3
CLK3B
Pin Configuration
C Y2X P 3 0 4 3 6 V F B G A P IN C O N F IG U R A T IO N
T O P V IE W
CLK 0
6
5
VDDA
GND
4
Xo u t
3
Xin
2
VDDB
1
A
CLK 0B
GND
S E R_D
A TA
S E R_CL
K
GND
VDDB
B
CLK 1
CLK 1B
CLK 2
T O P V IE W
GND
GND
GND
C
P LL_M UL
T
D
CLK _S E
L
E
CLK 2B
GND
GND
IN A
F
CLK 3
GND
V DDB
VDDB
GND
IN A B
G
CLK 3B
V DDA
V DDA
NC
VDDA
VDDA
H
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07589 Rev. *B
Revised July 28, 2004