CY2XL11_11 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 100 MHz LVDS Clock Generator Output frequency: 100 MHz

CY2XL11
100 MHz LVDS Clock Generator
Features
■ One low-voltage differential signaling (LVDS) output pair
■ Output frequency: 100 MHz
■ External crystal frequency: 25 MHz
■ Low RMS phase jitter at 100 MHz, using 25 MHz crystal
(637 kHz to 10 MHz): 0.53 ps (typical)
■ Pb-free 8-Pin TSSOP package
■ Supply voltage: 3.3 V or 2.5 V
■ Commercial temperature range
Logic Block Diagram
XIN
External
Crystal
Crystal
Oscillator
XOUT
Functional Description
The CY2XL11 is a PLL based high performance clock generator
with a crystal oscillator interface and one LVDS output pair. It is
optimized to generate PCI Express, FC, and other high-
performance clock frequencies. It also produces an output
frequency that is four times the crystal frequency. It uses
Cypress’s low-noise VCO technology to achieve less than 1 ps
typical RMS phase jitter, that meets high-performance systems’
jitter requirements.
Low-Noise PLL
Output
Divider
CLK
CLK#
OE
Pinouts
Figure 1. Pin Diagram - 8-Pin TSSOP
VDD 1
VSS 2
XOUT 3
XIN 4
8
VDD
7
CLK
6
CLK#
5
OE
Table 1. Pin Definition – 8-Pin TSSOP
Pin Number
1, 8
2
Pin Name
VDD
VSS
I/O Type
Power
Power
3, 4
XOUT, XIN
XTAL output and input
5
OE
CMOS input
6,7
CLK#, CLK
LVDS output
Description
3.3 V or 2.5 V power supply. All supply current flows through pin 1
Ground
Parallel resonant crystal interface
Output enable. When HIGH, the output is enabled. When LOW, the
output is high-impedance
Differential clock output
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-42886 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 18, 2011
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