CY2XF33_11 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – High-Performance LVDS Oscillator With Frequency Margining – Pin Control

CY2XF33
High-Performance LVDS Oscillator With
Frequency Margining – Pin Control
Features
■ Low jitter crystal oscillator (XO)
■ Less than 1 ps typical RMS phase jitter
■ Differential LVDS output
■ Output frequency from 50 MHz to 690 MHz
■ Two frequency margining control pins (FS0, FS1)
■ Factory configured or field programmable
■ Integrated phase-locked loop (PLL)
■ Supply voltage: 3.3 V or 2.5 V
■ Pb-free package: 5.0 × 3.2 mm LCC
■ Commercial and industrial temperature ranges
Logic Block Diagram
Functional Description
The CY2XF33 is a high-performance and high-frequency crystal
oscillator (XO). It uses a Cypress proprietary low-noise PLL to
synthesize the frequency from an integrated crystal. The output
frequency can be changed through two select pins, allowing
easy frequency margin testing in applications.
The CY2XF33 is available as a factory configured device or as
a field programmable device.
FS1 1
FS0 2
Crystal
Oscillator
Low-Noise PLL
Output
Divider
Frequency Select
Decode
4 CLK
5 CLK#
Pinouts
Figure 1. Pin Diagram – 6-Pin Ceramic LCC
FS1 1
FS0 2
VSS 3
6 VDD
5 CLK#
4 CLK
Table 1. Pin Definitions – 6-Pin Ceramic LCC
Pin
1, 2
4, 5
6
3
Name
FS1, FS0
CLK, CLK#
VDD
VSS
I/O Type
CMOS input
LVDS output
Power
Power
Frequency select
Differential output clock
Supply voltage: 2.5 V or 3.3 V
Ground
Description
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-53148 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 13, 2011