CY2V9950 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer

CY2V9950
2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer
Features
• 2.5V or 3.3V operation
• Split output bank power supplies
• Output frequency range: 6 MHz to 200 MHz
• Output-output skew < 150 ps
• Cycle-cycle jitter < 100 ps
• Selectable positive or negative edge synchronization
• Selectable phase-locked loop (PLL) frequency range
• 8 LVTTL outputs driving 50Ω terminated lines
• LVCMOS/LVTTL Over-voltage tolerant reference input
• 2x, 4x multiply and (1/2)x, (1/4)x divide ratios
• Spread-Spectrum-compatible
• Pin-compatible with IDT5V9950 and IDT5T9950
• Industrial temperature range: –40°C to +85°C
• 32-pin TQFP package
Block Diagram
Functional Description
The CY2V9950 is a low-voltage, low-power, eight-output,
200-MHz clock driver. It features functions necessary to
optimize the timing of high performance computer and
communication systems.
The user can program the output banks through 3F[0:1] and
4F[0:1]pins. Any one of the outputs can be connected to
feedback input to achieve different reference frequency multi-
plication and divide ratios and zero input-output delay.
The device also features split output bank power supplies
which enable the user to run two banks (1Qn and 2Qn) at a
power supply level different from that of the other two banks
(3Qn and 4Qn). Additionally, the PE pin controls the synchro-
nization of the output signals to either the rising or the falling
edge of the reference clock.
Pin Configuration
REF
FB
1F1:0
2F1:0
3F1:0
4F1:0
TEST PE FS VDDQ1
3
3
PLL
1Q0
1Q1
2Q0
2Q1
3
3
/K
3
/M
3
3Q0
3Q1
VDDQ3
4Q0
4Q1
VDDQ4 sOE#
3F1
4F0
4F1
PE
VDDQ4
4Q1
4Q0
VSS
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4
5
CY2V9950
21
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
1F1
1F0
sOE#
VDDQ1
1Q0
1Q1
VSS
VSS
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07436 Rev. *A
Revised August 11, 2004