CY2SSTV8575 Datasheet, PDF (1/8 Pages) SpectraLinear Inc – Differential Clock Buffer/Driver

TV8575
Features
• Operating frequency: 60 MHz to 170 MHz
• Supports 266-MHz DDR SDRAM
• 5 differential outputs from 1 differential input
• Spread Spectrum compatible
• Low jitter (cycle-to-cycle): < 75
• Very low skew: < 100 ps
• Power Management Control input
• High-impedance outputs when input clock < 20 MHz
• 2.5V operation
• 32-pin TQFP JEDEC MS-026 C
Block Diagram
CY2SSTV8575
Differential Clock Buffer/Driver
Description
The CY2SSTV8575 is a high-performance, low-skew, low jitter
zero-delay buffer designed to distribute differential clocks in
high-speed applications. The CY2SSTV8575 generates five
differential pair clock outputs from one differential pair clock
input. In addition, the CY2SSTV8575 features differential
feedback clock outputs and inputs. This allows the
CY2SSTV8575 to be used as a zero-delay buffer.
When used as a zero-delay buffer in nested clock trees, the
CY2SSTV8575 locks onto the input reference and translates
with near zero delay to low-skew outputs.
Pin Configuration
OE ²³
AVDD ⁸
Test and
Powerdown
Logic
CLK ⁵
CLK# ⁶
FBIN ₂₁
PLL
FB#I 22
N
2 _Y0
1 _Y0#
12 _Y1
11 _Y1#
15 _Y2
16 _Y2#
27 _Y3
28 _Y3#
30 _Y4
31 _Y4#
18 _FBOUT
19 _FBOUT#
VSS
VDDQ
Y3
Y3#
VDDQ
Y4
Y4#
VSS
24 23 22 21 20 19 18 17
CY2SSTV8575
TQFP-32
JEDEC MS-026 C
12345678
Y2#
Y2
VSS
VDDQ
Y1
Y1#
VSS
AVSS
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07458 Rev. **
Revised October 30, 2002