CY2SSTV855_06 Datasheet, PDF (1/7 Pages) Cypress Semiconductor – Differential Clock Buffer/Driver

CY2SSTV855
Differential Clock Buffer/Driver
Features
• Phase-locked loop (PLL) clock distribution for Double
Data Rate Synchronous DRAM applications
• 1:5 differential outputs
• External feedback pins (FBINT, FBINC) are used to
synchronize the outputs to the clock input
• SSCG: Spread Aware™ for electromagnetic
interference (EMI) reduction
• 28-pin TSSOP package
• Conforms to JEDEC DDR specifications
Functional Description
The CY2SSTV855 is a high-performance, very-low-skew,
very-low-jitter zero-delay buffer that distributes a differential
clock input pair (SSTL_2) to four differential (SSTL_2) pairs of
clock outputs and one differential pair of feedback clock
outputs. In support of low power requirements, when
power-down is HIGH, the outputs switch in phase and
frequency with the input clock. When power-down is LOW, all
outputs are disabled to a high-impedance state and the PLL is
shut down.
The device supports a low-frequency power-down mode.
When the input is < 20 MHz, the PLL is disabled and the
outputs are put in the Hi-Z state. When the input frequency is
> 20 MHz, the PLL and outputs are enabled.
When AVDD is tied to ground, the PLL is turned off and
bypassed with the input reference clock gated to the outputs.
The Cypress CY2SSTV855 is Spread Aware and supports
tracking of Spread Spectrum clock inputs to reduce EMI
Block Diagram
Pin Configuration
PWRDWN
AVDD
Powerdown
and test
logic
CLKINT
CLKINC
PLL
FBINT
FBINC
YT0
YC0
YT1
YC1
YT2
YC2
YT3
YC3
FBOUTT
FBOUTC
GND 1
YC0 2
YT0 3
VDDQ ₄
GND 5
CLKINT ₆
CLKINC ₇
VDDQ ₈
AVDD ₉
AGND ₁₀
VDDQ 11
YT1 ₁₂
YC1 ₁₃
GND ₁₄
28 GND
27 YC3
26 YT3
25 VDDQ
24 ^PWRDWN
23 ^FBINT
22 ^FBINC
21 ^VDDQ
20 ^FBOUTC
19 ^FBOUTT
18 ^VDDQ
17 ^YT2
16 ^YC2
15 ^GND
28-pin TSSOP
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-07459 Rev. *F
Revised January 2, 2006