CY2SSTV16859 Datasheet, PDF (1/8 Pages) Cypress Semiconductor – 13-Bit to 26-Bit Registered Buffer PC2700-/PC3200-Compliant

CY2SSTV16859
13-Bit to 26-Bit Registered Buffer
PC2700-/PC3200-Compliant
Features
• Differential clock inputs up to 280 MHz
• Supports LVTTL switching levels on the RESET# pin
• Output drivers have controlled edge rates, so no
external resistors are required.
• Two KV ESD protection
• Latch-up performance exceeds 100 mA per JESD78,
Class II
• 64-pin TSSOP/JEDEC and 56-pin QFN package avail-
ability
• JEDEC specification supported
Description
This 13-bit to 26-bit registered buffer is designed for 2.3V to
2.7 VDD operations.
All inputs are compatible with the JEDEC Standard for SSTL-2,
except the LVCMOS reset (RESET#) input. All outputs are
SSTL_2, Class II compatible.
The CY2SSTV16859 operates from a differential clock (CLK
and CLK#) of frequency up to 280 MHz. Data are registered at
crossing of CLK going high and CLK# going low.
When RESET# is low, the differential input receivers are
disabled, and undriven (floating) data and clock inputs are
allowed. The LVCMOS RESET# input must always be held at
a valid logic high or low level.
To ensure defined outputs from the register before a stable
clock has been supplied, RESET# must be held in the low
state during power up.
In the DDR DIMM application, RESET# is completely
asynchronous with respect to CLK# and CLK. Therefore, no
timing relationship can be guaranteed between the two. When
entering reset, the register is cleared and the outputs are
driven low quickly, relative to the time to disable the differential
input receivers, thus ensuring no glitches on the output.
However, when coming out of reset, the register becomes
active quickly, relative to the time to enable the differential
input receivers.
Block Diagram
Pin Configuration
RESET #
CLK
CLK #
D1
VREF
D
Q1A
C
Q1B
R
To 12 Other Channels
Q13A 1
Q12A 2
Q11A 3
Q10A 4
Q9A 5
VDDQ 6
GND 7
Q8A 8
Q7A 9
Q6A 10
Q5A 11
Q4A 12
Q3A 13
Q2A 14
GND 15
Q1A 16
Q13B 17
VDDQ 18
Q12B 19
Q11B 20
Q10B 21
Q9B 22
Q8B 23
Q7B 24
Q6B 25
GND 26
VDDQ 27
Q5B 28
Q4B 29
Q3B 30
Q2B 31
Q1B 32
64 VDDQ
63 GND
62 D13
61 D12
60 VDD
59 VDDQ
58 GND
57 D11
56 D10
55 D9
54 GND
53 D8
52 D7
51 RESET #
50 GND
49 CLK #
48 CLK
47 VDDQ
46 VDD
45 VREF
44 D6
43 GND
42 D5
41 D4
40 D3
39 GND
38 VDDQ
37 VDD
36 D2
35 D1
34 GND
33 VDDQ
64 TSSOP Package
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07463 Rev. *B
Revised July 29, 2003