CY2SSTV16857 Datasheet, PDF (1/8 Pages) SpectraLinear Inc – 14-Bit Regstered Buffer PC2700-/PC3200-Compliant

CY2SSTV16857
Features
• Differential Clock Inputs up to 280 MHz
• Supports LVTTL switching levels on the RESET pin
• Output drivers have controlled edge rates, so no
external resistors are required
• Two KV ESD protection
• Latch-up performance exceeds 100 mA: JESD78, Class II
• Conforms to JEDEC STD (JESD82-3) for buffered DDR
DIMMs
• 48-pin TSSOP
Description
This 14-bit registered buffer is designed specifically for 2.3V to
2.7V V_DD operation and is characterized for operation from
0°C to + 85°C.
All inputs are compatible with the JEDEC Standard for
SSTL_2, except the LVCMOS reset (RESET) input. All outputs
are SSTL_2, Class II-compatible.
The SSTV16857 operates from a differential clock (CLK and
CLK). Data is measured at the crossing of CLK going HIGH,
and CLK going LOW.
14-Bit Registered Buffer
PC2700-/PC3200-Compliant
When RESET is LOW, the differential input receivers are
disabled, and undriven (floating) data, clock, and REF voltage
inputs are allowed. In addition, when RESET is LOW, all
registers are reset and all outputs force to the LOW state. The
LVCMOS RESET input must always be held at a valid logic
HIGH or LOW level.
To ensure defined outputs from the register before a stable
clock has been supplied, RESET must be held in the LOW
state during power-up.
In the DDR registered DIMM application, RESET is specified
to be completely asynchronous with respect to CLK and CLK.
Therefore, no timing relationship can be guaranteed between
the two. When entering reset, the register will be cleared and
the outputs will be driven LOW quickly, relative to the time to
disable the differential input receivers, thus ensuring no
glitches on the output. However, when coming out of reset, the
register will become active quickly, relative to the time to
enable the differential input receivers. As long as the data
inputs are low, and the clock is stable during the time from the
LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design must ensure that the outputs will
remain LOW.
Block Diagram
Pin Configuration
RESET
CLK
CLK
VREF
D1
1D
C1
Q1
R
To 13 Other Channels
Q1 1
Q2 2
VSS 3
VDDQ 4
Q3 5
Q4 6
Q5 7
VSS 8
VDDQ 9
Q6 10
Q7 11
VDDQ 12
VSS 13
Q8 14
Q9 15
VDDQ 16
VSS 17
Q10 18
Q11 19
Q12 20
VDDQ 21
VSS 22
Q13 23
Q14 24
48 D1
47 D2
46 VSS
45 VDD
44 D3
43 D4
42 D5
41 D6
40 D7
39 CLK
38 CLK
37 VDD
36 VSS
35 VREF
34 RESET
33 D8
32 D9
31 D10
30 D11
29 D12
28 VDD
27 VSS
26 D13
25 D14
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07443 Rev. *D
Revised January 12, 2005