CY2PP3115 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – 1:15 Differential Fanout Buffer

PRELIMINARY
FastEdge™ Series
CY2PP3115
1:15 Differential Fanout Buffer
Features
• Fifteen ECL/PECL differential outputs grouped in four
banks
• Two ECL/PECLdifferential inputs
• Hot-swappable/-insertable
• 50-ps output-to-output skew
• < 200-ps device-to-device skew
• Less than 2-pS intrinsic jitter
• < 500-ps propagation delay (typical)
• Operation up to 1.5 GHz
• PECL mode supply range: V_CC = 2.375V to 3.465V with
V_EE = 0V
• ECL mode supply range: V_EE = –2.375V to –3.465V with
V_CC = 0V
• Industrial temperature range: –40^°C to 85^°C
• 52-pin 1.4mm TQFP package
• Temperature compensation like 100K ECL
Block Diagram
FSELA
VEE
VCC
CLK0
CLK0#
0
VCC ^VEE
1
CLK1
CLK1#
CLK_SEL
VEE
VEE
FSELB
FSELC
MR
VEE
VEE
FSELD
VEE
0
1
/1
0
/2
1
0
1
0
1
Description
The CY2PP3115 is a low-skew, low propagation delay 1-to-15
differential fanout buffer targeted to meet the requirements of
high-performance clock and data distribution applications. The
device is implemented on SiGe technology and has a fully
differential internal architecture that is optimized to achieve
low-signal skews at operating frequencies of up to 1.5 GHz.
The device features two differential input paths which are
multiplexed internally. This mux is controlled by the CLK_SEL
pin. The CY2PP3115 may function not only as a differential
clock buffer but also as a signal level translator and fanout on
ECL/PECL single-ended signal to 15 ECL/PECL differential
loads. An external bias pin, VBB, is provided for this purpose.
In such an application, the VBB pin should be connected to
either one of the CLKA# or CLKB# inputs and bypassed to V_CC
via a 0.01-µF capacitor.
Since the CY2PP3115 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in
communication systems. Furthermore, advanced circuit
design schemes, such as internal temperature compensation,
ensure that the CY2PP3115 delivers consistent, guaranteed
performance over differing platforms.
Pin Configuration
QAO
QA1
QBO
QB1
QB2
QC0
QC1
QC2
QC3
QD0
QD1
QD2
QD3
QD4
QD5
VBB
VCC 1
MR 2
FSELA 3
FSELB 4
CLK0 5
CLK0# 6
CLK_SEL 7
CLK1 8
CLK1# 9
VBB 10
FSELC 11
FSELD 12
VEE 13
CY2PP3115
39 VCC
38 QC0
37 QC0#
36 QC1
35 QC1#
34 QC2
33 QC2#
32 QC3
31 QC3#
30 VCC
29 NC
28 NC
27 VCC
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07502 Rev.*A
Revised November 18, 2003