CY2PD817 Datasheet, PDF (1/6 Pages) Cypress Semiconductor – 320-MHz 1:7 PECL to PECL/CMOS Buffer

CY2PD817
320-MHz 1:7 PECL to PECL/CMOS Buffer
Features
• DC to 320-MHz operation
• 50-ps output-output skew
• 30-ps cycle-cycle jitter
• 2.5V power supply
• LVPECL input @ 320-MHz Operation
• One LVPECL output @ 320-MHz Operation
• Four LVCMOS/LVTTL outputs @ 250 MHz/160 MHz
• Two LVCMOS/LVTTL outputs @ 250 MHz/80 MHz
• 45% to 55% output duty cycle
• Output divider control
• Output enable/disable control
• Operating temperature range: 0°C to +85°C
• 24-pin TSSOP
Description
The CY2PD817 is a low-voltage LVPECL-to-LVPECL and
LVCMOS fanout buffer designed for servers, data communi-
cations, and clock management.
The CY2PD817 is ideal for applications requiring mixed differ-
ential and single-ended clock distribution. This device accepts
an LVPECL input reference clock and provides one LVPECL
and six LVCMOS/LVTTL output clocks. The outputs are parti-
tioned into three banks of one, two, and four outputs. The
LVPECL output is a buffered copy of the input clock while the
LVCMOS outputs are divided by 1, 2, and 4. When CLRDIV is
set HIGH, the output dividers are set to 1. In this mode, the
maximum input frequency is limited to 250 MHz.
When OE is set HIGH, the outputs are disabled in a High-Z
state.
Block Diagram
PCLKI
PCLKI
CLRDIV
OE
÷ 4, ÷ 1
÷ 2, ÷ 1
PCLKO
PCLKO
QA[0:1]
QB[0:3]
Pin Configuration
VDD 1
PCLKI 2
PCLKI ₃
VSS ₄
VDD ₅
PCLKO ₆
PCLKO ₇
VSS ₈
OE ₉
VDD ₁₀
VSS 11
CLRDIV ₁₂
24 VDD
23 ^QA0
22 QA1
21 VSS
20 ^VDD
19 ^QB0
18 ^QB1
17 ^VSS
16 ^VDD
15 ^QB2
14 ^QB3
13 ^VSS
24 TSSOP
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07574 Rev. **
Revised August 28, 2003