CY2DP818_12 Datasheet, PDF (1/13 Pages) Cypress Semiconductor – 1:8 Clock Fanout Buffer

CY2DP818
1:8 Clock Fanout Buffer
1:8 Clock Fanout Buffer
Features
■ Low-voltage operation V_DD = 3.3 V
■ 1:8 fanout
■ Operation to350 MHz
■ Single input configurable for LVDS, LVPECL, or LVTTL
■ 8 pair of LVPECL outputs
■ Drives a 50 ohm load
■ Low input capacitance
■ Low output skew
■ Low propagation delay (tpd = 4 ns, typical)
■ Commercial and Industrial temperature ranges
■ 38-pin TSSOP Package
Logic Block Diagram
INPUT
(LVPECL / LVDS / LVTTL)
INPUT A
INPUT B
InConfig
Description
The Cypress CY2DP818 fanout buffer features a single LVDS or
a single ended LVTTL compatible input and eight LVPECL output
pairs.
Designed for data-communications clock management
applications, the large fanout from a single input reduces loading
on the input clock.
The CY2DP818 is ideal for both level translations from single
ended to LVPECL and/or for the distribution of LVPECL based
clock signals.
The Cypress CY2DP818 has configurable input functions. The
input is user configurable via the InConfig pin for single ended or
differential input.
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
Q5A
Q5B
Q6A
Q6B
Q7A
Q7B
Q8A
Q8B
OUTPUT
(LVPECL)
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07061 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 20, 2012