CY2DP818 Datasheet, PDF (1/8 Pages) Cypress Semiconductor – 1:8 Clock Fanout Buffer

ComLink™ Series
CY2DP818
1:8 Clock Fanout Buffer
Features
• Low-voltage operation V_DD = 3.3V
• 1:8 fanout
• Single-input-configurable for LVDS, LVPECL, or LVTTL
• 8 pair of LVPECL outputs
• Drives a 50-ohm load
• Low input capacitance
• Low output skew
• Low propagation delay Typical (tpd < 4 ns)
• Industrial versions available
• Package available include: TSSOP
• Does not exceed Bellcore 802.3 standards
• Operation at ⇒ 350 MHz–700 Mbps
Description
This Cypress series of network circuits are produced using
advanced 0.35-micron CMOS technology, achieving the
industry’s fastest logic.
The Cypress CY2DP818 fanout buffer features a single LVDS
or a single-ended LVTTL-compatible input and eight LVPECL
output pairs.
Designed for data-communications clock-management appli-
cations, the large fanout from a single input reduces loading
on the input clock.
The CY2DP818 is ideal for both level translations from
single-ended to LVPECL and/or for the distribution of
LVPECL-based clock signals.
The Cypress CY2DP818 has configurable input functions. The
input is user configurable via the Inconfig pin for single ended
or differential input.
Block Diagram
Pin Configuration
INPUT
(LVPECL / LVDS / LVTTL)
INPUT A
INPUT B
InConfig
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
Q5A
Q5B
Q6A
Q6B
Q7A
Q7B
Q8A
Q8B
OUTPUT
(LVPECL)
GND ₁
VDD 2
VDD 3
VDD 4
VDD 5
VDD ₆
InConfig ₇
VDD ₈
GND 9
INPUT A 10
INPUT B 11
GND 12
VDD 13
VDD ₁₄
VDD ₁₅
VDD 16
VDD ₁₇
GND 18
GND 19
38 ^GND
37 ^Q1A
36 ^Q1B
35 ^Q2A
34 ^Q2B
33 ^Q3A
32 ^Q3B
31 ^Q4A
30 ^Q4B
29 ^VDD
28 ^Q5A
27 ^Q5B
26 ^Q6A
25 ^Q6B
24 ^Q7A
23 ^Q7B
22 ^Q8A
21 Q8B
20 GND
38-pin TSSOP
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07061 Rev. *A
Revised July 9, 2002