CY2DP814 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 1:4 Clock Fanout Buffer

ComLink™ Series
CY2DP814
1:4 Clock Fanout Buffer
Features
• Low voltage operation
• V_DD = 3.3V
• 1:4 fanout
• Single-input configurable for LVDS, LVPECL, or LVTTL
• Four differential pairs of LVPECL outputs
• Drives 50-ohm load
• Low input capacitance
• Low output skew
• Low propagation delay
— Typical (tpd < 4 ns)
• Industrial versions available
• Available packages include TSSOP, SOIC
Description
The Cypress CY2 series of network circuits are produced
using advanced 0.35-micron CMOS technology, achieving the
industry’s fastest logic.
The Cypress CY2DP814 fanout buffer features a single LVDS-
or a single LVPECL-compatible input and four LVPECL output
pairs.
Designed for data communications clock management appli-
cations, the fanout from a single input reduces loading on the
input clock.
The CY2DP814 is ideal for both level translations from
single-ended to LVPECL and/or for the distribution of
LVDS-based clock signals. The Cypress CY2DP814 has
configurable input between logic families. The input can be
selectable for an LVPECL/LVTTL or LVDS signal, while the
output drivers support LVPECL capable of driving 50-ohm
lines.
Block Diagram
Pin Configuration
EN1 1
EN2 8
IN+ 6
IN- 7
LVDS /
LVPECL /
LVTTL
CONFIG 2
16 Q1A
15 Q1B
14 Q2A
13 Q2B
12 Q3A
11 Q3B
10 Q4A
9 Q4B
OUTPUT
LVPECL
EN1 ₁
CONFIG ₂
VDD ₃
VDD ₄
GND ₅
IN+ ₆
IN- ₇
EN2 ₈
16 Q1A
15 Q1B
14 Q2A
13 Q2B
12 Q3A
11 Q3B
10 Q4A
9 Q4B
16 pin TSSOP / SOIC
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07060 Rev. *B
Revised December 15, 2002